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From: sashiko-bot@kernel.org
To: "Abel Vesa" <abel.vesa@oss.qualcomm.com>
Cc: devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org,
	krzk+dt@kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block
Date: Thu, 14 May 2026 04:15:04 +0000	[thread overview]
Message-ID: <20260514041505.3F94FC2BCB7@smtp.kernel.org> (raw)
In-Reply-To: <20260513-eliza-llcc-v2-1-27381ae833d5@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `reg` and `reg-names` properties for `qcom,eliza-llcc` incorrectly skip `llcc1_base` and define `llcc2_base` as the second base register region.
--

commit b822a325e6d0b593e6e849500133d7b473e7127e
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

This commit documents the Last Level Cache Controller (LLCC) for the Eliza
SoC. It specifies that the Eliza LLCC block has 2 base register regions
and an additional AND/OR broadcast region.

> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml

[ ... ]

> @@ -341,6 +342,27 @@ allOf:
>              - const: llcc_broadcast_base
>              - const: llcc_broadcast_and_base
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,eliza-llcc
> +    then:
> +      properties:
> +        reg:
> +          items:
> +            - description: LLCC0 base register region
> +            - description: LLCC2 base register region
> +            - description: LLCC broadcast OR register region
> +            - description: LLCC broadcast AND register region
> +        reg-names:
> +          items:
> +            - const: llcc0_base
> +            - const: llcc2_base

The commit message mentions that Eliza LLCC has 2 base register regions,
but the names here skip to llcc2_base. Should this be llcc1_base instead?

Looking at the upstream LLCC driver (drivers/soc/qcom/llcc-qcom.c), it
maps base register regions by their sequential index and generates internal
regmap names sequentially.

If the driver fetches the second region at index 1, it will internally
name it llcc1_base, which creates a semantic mismatch with the device
tree's llcc2_base designation.

Could this also lead to an out-of-bounds mapping if the hardware
dynamically reports 3 banks?

> +            - const: llcc_broadcast_base
> +            - const: llcc_broadcast_and_base

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260513-eliza-llcc-v2-0-27381ae833d5@oss.qualcomm.com?part=1

  reply	other threads:[~2026-05-14  4:15 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-13 11:11 [PATCH v2 0/2] soc: qcom: llcc-qcom: Add support for Eliza and document bindings Abel Vesa
2026-05-13 11:11 ` [PATCH v2 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block Abel Vesa
2026-05-14  4:15   ` sashiko-bot [this message]
2026-05-13 11:11 ` [PATCH v2 2/2] soc: qcom: llcc-qcom: Add support for Eliza Abel Vesa
2026-05-14  4:30   ` sashiko-bot

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