[PATCH v2 0/2] soc: qcom: llcc-qcom: Add support for Eliza and document bindings

[PATCH v2 0/2] soc: qcom: llcc-qcom: Add support for Eliza and document bindings

[Abel Vesa]

Add support for the Last Level Cache Controller found on the Qualcomm
Eliza SoC.

Eliza's LLCC uses a 4-region register layout, with two per-bank base
regions plus the broadcast OR and AND windows.

Describe that layout in the devicetree bindings and add the corresponding
slice configuration and driver data in llcc-qcom.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
Changes in v2:
- Rebased on next-20260508.
- Replaced the weird phrase in the last commit with something
  more sane.
- Picked up Konrad's R-b tag for the second patch.
- Link to v1: https://patch.msgid.link/20260504-eliza-llcc-v1-0-d7006c899812@oss.qualcomm.com

---
Abel Vesa (2):
      dt-bindings: cache: qcom,llcc: Document Eliza LLCC block
      soc: qcom: llcc-qcom: Add support for Eliza

 .../devicetree/bindings/cache/qcom,llcc.yaml       |  22 +++
 drivers/soc/qcom/llcc-qcom.c                       | 180 +++++++++++++++++++++
 2 files changed, 202 insertions(+)
---
base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83
change-id: 20260428-eliza-llcc-312b07fefc10

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>

[PATCH v2 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Abel Vesa]

Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
base register regions and an additional AND, OR broadcast region, total 4
register regions.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 .../devicetree/bindings/cache/qcom,llcc.yaml       | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index 995d57815781..90f5a54b76e3 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -20,6 +20,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,eliza-llcc
       - qcom,glymur-llcc
       - qcom,ipq5424-llcc
       - qcom,kaanapali-llcc
@@ -341,6 +342,27 @@ allOf:
             - const: llcc_broadcast_base
             - const: llcc_broadcast_and_base
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,eliza-llcc
+    then:
+      properties:
+        reg:
+          items:
+            - description: LLCC0 base register region
+            - description: LLCC2 base register region
+            - description: LLCC broadcast OR register region
+            - description: LLCC broadcast AND register region
+        reg-names:
+          items:
+            - const: llcc0_base
+            - const: llcc2_base
+            - const: llcc_broadcast_base
+            - const: llcc_broadcast_and_base
+
 additionalProperties: false
 
 examples:

-- 
2.54.0

Re: [PATCH v2 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `reg` and `reg-names` properties for `qcom,eliza-llcc` incorrectly skip `llcc1_base` and define `llcc2_base` as the second base register region.
--

commit b822a325e6d0b593e6e849500133d7b473e7127e
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

This commit documents the Last Level Cache Controller (LLCC) for the Eliza
SoC. It specifies that the Eliza LLCC block has 2 base register regions
and an additional AND/OR broadcast region.

> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml

[ ... ]

> @@ -341,6 +342,27 @@ allOf:
>              - const: llcc_broadcast_base
>              - const: llcc_broadcast_and_base
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,eliza-llcc
> +    then:
> +      properties:
> +        reg:
> +          items:
> +            - description: LLCC0 base register region
> +            - description: LLCC2 base register region
> +            - description: LLCC broadcast OR register region
> +            - description: LLCC broadcast AND register region
> +        reg-names:
> +          items:
> +            - const: llcc0_base
> +            - const: llcc2_base

The commit message mentions that Eliza LLCC has 2 base register regions,
but the names here skip to llcc2_base. Should this be llcc1_base instead?

Looking at the upstream LLCC driver (drivers/soc/qcom/llcc-qcom.c), it
maps base register regions by their sequential index and generates internal
regmap names sequentially.

If the driver fetches the second region at index 1, it will internally
name it llcc1_base, which creates a semantic mismatch with the device
tree's llcc2_base designation.

Could this also lead to an out-of-bounds mapping if the hardware
dynamically reports 3 banks?

> +            - const: llcc_broadcast_base
> +            - const: llcc_broadcast_and_base

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260513-eliza-llcc-v2-0-27381ae833d5@oss.qualcomm.com?part=1

[PATCH v2 2/2] soc: qcom: llcc-qcom: Add support for Eliza

[Abel Vesa]

Eliza uses a 4-region LLCC register layout made up of two per-bank base
register regions together with the broadcast OR and AND regions.

So add this SoC specific configuration and its compatible string.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/soc/qcom/llcc-qcom.c | 180 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 180 insertions(+)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 0161ceec8842..7c05cb3619b2 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -181,6 +181,171 @@ enum llcc_reg_offset {
 	LLCC_TRP_WRS_CACHEABLE_EN,
 };
 
+static const struct llcc_slice_config eliza_data[] = {
+	{
+		.usecase_id = LLCC_CPUSS,
+		.slice_id = 1,
+		.max_cap = 896,
+		.bonus_ways = 0xfff,
+		.activate_on_init = true,
+		.write_scid_en = true,
+		.stale_en = true,
+	},
+	{
+		.usecase_id = LLCC_MDMHPFX,
+		.slice_id = 24,
+		.max_cap = 1024,
+		.priority = 5,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+	},
+	{
+		.usecase_id = LLCC_VIDSC0,
+		.slice_id = 2,
+		.max_cap = 128,
+		.priority = 5,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+	},
+	{
+		.usecase_id = LLCC_MDMHPGRW,
+		.slice_id = 25,
+		.max_cap = 1024,
+		.priority = 5,
+		.bonus_ways = 0xfff,
+	},
+	{
+		.usecase_id = LLCC_GPUHTW,
+		.slice_id = 11,
+		.max_cap = 256,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+	},
+	{
+		.usecase_id = LLCC_GPU,
+		.slice_id = 9,
+		.max_cap = 896,
+		.priority = 1,
+		.bonus_ways = 0xfff,
+		.write_scid_cacheable_en = true,
+	},
+	{
+		.usecase_id = LLCC_MMUHWT,
+		.slice_id = 18,
+		.max_cap = 256,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.activate_on_init = true,
+	},
+	{
+		.usecase_id = LLCC_MDMPNG,
+		.slice_id = 27,
+		.max_cap = 256,
+		.priority = 5,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+	},
+	{
+		.usecase_id = LLCC_MODPE,
+		.slice_id = 29,
+		.max_cap = 256,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xf00,
+		.alloc_oneway_en = true,
+	},
+	{
+		.usecase_id = LLCC_WRCACHE,
+		.slice_id = 31,
+		.max_cap = 256,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.activate_on_init = true,
+	},
+	{
+		.usecase_id = LLCC_LCPDARE,
+		.slice_id = 30,
+		.max_cap = 128,
+		.priority = 5,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.activate_on_init = true,
+		.alloc_oneway_en = true,
+	},
+	{
+		.usecase_id = LLCC_ISLAND1,
+		.slice_id = 12,
+		.max_cap = 1280,
+		.priority = 7,
+		.fixed_size = true,
+		.res_ways = 0x3ff,
+	},
+	{
+		.usecase_id = LLCC_CAMOFE,
+		.slice_id = 33,
+		.max_cap = 1024,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.stale_en = true,
+		.parent_slice_id = 13,
+	},
+	{
+		.usecase_id = LLCC_CAMRTIP,
+		.slice_id = 13,
+		.max_cap = 1024,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.stale_en = true,
+		.parent_slice_id = 13,
+	},
+	{
+		.usecase_id = LLCC_CAMSRTIP,
+		.slice_id = 14,
+		.max_cap = 512,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.stale_en = true,
+		.parent_slice_id = 13,
+	},
+	{
+		.usecase_id = LLCC_CAMRTRF,
+		.slice_id = 7,
+		.max_cap = 1024,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.stale_en = true,
+		.parent_slice_id = 13,
+	},
+	{
+		.usecase_id = LLCC_CAMSRTRF,
+		.slice_id = 21,
+		.max_cap = 1024,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.stale_en = true,
+		.parent_slice_id = 13,
+	},
+	{
+		.usecase_id = LLCC_CPUSSMPAM,
+		.slice_id = 6,
+		.max_cap = 512,
+		.priority = 0,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.activate_on_init = true,
+		.write_scid_en = true,
+		.stale_en = true,
+	},
+};
+
 static const struct llcc_slice_config glymur_data[] = {
 	{
 		.usecase_id = LLCC_CPUSS,
@@ -4141,6 +4306,15 @@ static const u32 llcc_v6_reg_offset[] = {
 	[LLCC_TRP_WRS_CACHEABLE_EN]	= 0x00042088,
 };
 
+static const struct qcom_llcc_config eliza_cfg[] = {
+	{
+		.sct_data	= eliza_data,
+		.size		= ARRAY_SIZE(eliza_data),
+		.reg_offset	= llcc_v6_reg_offset,
+		.edac_reg_offset = &llcc_v6_edac_reg_offset,
+	},
+};
+
 static const struct qcom_llcc_config kaanapali_cfg[] = {
 	{
 		.sct_data	= kaanapali_data,
@@ -4397,6 +4571,11 @@ static const struct qcom_llcc_config x1e80100_cfg[] = {
 	},
 };
 
+static const struct qcom_sct_config eliza_cfgs = {
+	.llcc_config	= eliza_cfg,
+	.num_config	= ARRAY_SIZE(eliza_cfg),
+};
+
 static const struct qcom_sct_config kaanapali_cfgs = {
 	.llcc_config	= kaanapali_cfg,
 	.num_config	= ARRAY_SIZE(kaanapali_cfg),
@@ -5238,6 +5417,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id qcom_llcc_of_match[] = {
+	{ .compatible = "qcom,eliza-llcc", .data = &eliza_cfgs },
 	{ .compatible = "qcom,glymur-llcc", .data = &glymur_cfgs },
 	{ .compatible = "qcom,ipq5424-llcc", .data = &ipq5424_cfgs},
 	{ .compatible = "qcom,kaanapali-llcc", .data = &kaanapali_cfgs},

-- 
2.54.0

Re: [PATCH v2 2/2] soc: qcom: llcc-qcom: Add support for Eliza

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Dynamically calculating `num_banks` creates a critical index-shifting vulnerability for `bcast_regmap` when combined with a static 4-region DT layout.
- [Medium] The LLCC_GPU slice configuration sets `.write_scid_cacheable_en = true` but omits `.write_scid_en = true`.
--

commit 33894fa3694ee52109e04ccbe94ee141b9842f00
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

soc: qcom: llcc-qcom: Add support for Eliza

This commit adds the SoC-specific configuration and compatible string for
Eliza. Eliza uses a 4-region LLCC register layout with two per-bank base
register regions and broadcast OR/AND regions.

> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 0161ceec88421..7c05cb3619b2d 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c

[ ... ]

> @@ -181,6 +181,171 @@ enum llcc_reg_offset {
> +	{
> +		.usecase_id = LLCC_GPU,
> +		.slice_id = 9,
> +		.max_cap = 896,
> +		.priority = 1,
> +		.bonus_ways = 0xfff,
> +		.write_scid_cacheable_en = true,
> +	},

The LLCC_GPU slice configures .write_scid_cacheable_en = true but omits
setting .write_scid_en = true. Without write_scid_en set, the corresponding
bit in the LLCC_TRP_WRS_EN register evaluates to 0 and is not enabled.

Without the hardware write allocator enabled for this SCID, could the
cacheable setting be rendered ineffective? Other comparable configurations
like glymur_data explicitly set both flags for the GPU slice.

[ ... ]

> @@ -4141,6 +4306,15 @@ static const u32 llcc_v6_reg_offset[] = {
>  	[LLCC_TRP_WRS_CACHEABLE_EN]	= 0x00042088,
>  };
>  
> +static const struct qcom_llcc_config eliza_cfg[] = {
> +	{
> +		.sct_data	= eliza_data,
> +		.size		= ARRAY_SIZE(eliza_data),
> +		.reg_offset	= llcc_v6_reg_offset,
> +		.edac_reg_offset = &llcc_v6_edac_reg_offset,
> +	},
> +};

Eliza uses a static 4-region Device Tree layout (llcc0, llcc1, bcast,
bcast_and). Since .num_banks is not hardcoded here, the driver will
dynamically read it from LLCC_COMMON_STATUS0.

If a defective bank is fused off on a lower-binned SKU, num_banks would be
read as 1. The probe function initializes regmaps based on num_banks:

qcom_llcc_probe() {
    ...
    for (i = 1; i < num_banks; i++) {
        ...
    }
    
    drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base");
    ...
}

If num_banks is 1, the loop exits with i = 1. The driver will then map
index 1 from the Device Tree to bcast_regmap. Since index 1 corresponds to
llcc1_base in a static 4-region layout, could this result in broadcast
commands being incorrectly written to the llcc1 base registers, causing
memory corruption and non-functional broadcasts?

Should .num_banks = 2 be explicitly hardcoded here to prevent this index
shifting, or should the driver be updated to map resources by name instead?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260513-eliza-llcc-v2-0-27381ae833d5@oss.qualcomm.com?part=2