* [PATCH 0/1] add SAR ADC DTS support for S32G2/S32G3 SoCs @ 2026-05-13 14:29 Khristine Andreea Barbulescu 2026-05-13 14:29 ` [PATCH 1/1] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3 Khristine Andreea Barbulescu 0 siblings, 1 reply; 3+ messages in thread From: Khristine Andreea Barbulescu @ 2026-05-13 14:29 UTC (permalink / raw) To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Frank Li, Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree, linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz, Enric Balletbo This patchset aims to add one change to the S32G2/S32G3 dtsi support: - Add SAR ADC dts support for S32G SoC based boards Khristine Andreea Barbulescu (1): arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3 arch/arm64/boot/dts/freescale/s32g2.dtsi | 24 +++++++++++++++++++++++- arch/arm64/boot/dts/freescale/s32g3.dtsi | 24 +++++++++++++++++++++++- 2 files changed, 46 insertions(+), 2 deletions(-) -- 2.34.1 ^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/1] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3 2026-05-13 14:29 [PATCH 0/1] add SAR ADC DTS support for S32G2/S32G3 SoCs Khristine Andreea Barbulescu @ 2026-05-13 14:29 ` Khristine Andreea Barbulescu 2026-05-14 5:42 ` sashiko-bot 0 siblings, 1 reply; 3+ messages in thread From: Khristine Andreea Barbulescu @ 2026-05-13 14:29 UTC (permalink / raw) To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Frank Li, Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree, linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz, Enric Balletbo Add ADC0 and ADC1 for S32G2 and S32G3 SoCs. Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 24 +++++++++++++++++++++++- arch/arm64/boot/dts/freescale/s32g3.dtsi | 24 +++++++++++++++++++++++- 2 files changed, 46 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 51d00dac12de..e69bd6222511 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright 2017-2021, 2024-2025 NXP + * Copyright 2017-2021, 2024-2026 NXP */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -554,6 +554,28 @@ i2c2: i2c@401ec000 { status = "disabled"; }; + adc0: adc@401f8000 { + compatible = "nxp,s32g2-sar-adc"; + reg = <0x401f8000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x41>; + dmas = <&edma0 0 32>; + dma-names = "rx"; + vref = <1800>; + status = "disabled"; + }; + + adc1: adc@402e8000 { + compatible = "nxp,s32g2-sar-adc"; + reg = <0x402e8000 0x1000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x41>; + dmas = <&edma1 1 32>; + dma-names = "rx"; + vref = <1800>; + status = "disabled"; + }; + swt4: watchdog@40200000 { compatible = "nxp,s32g2-swt"; reg = <0x40200000 0x1000>; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index e314f3c7d61d..1d48d8c47767 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2025 NXP + * Copyright 2021-2026 NXP * * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> * Ciprian Costea <ciprianmarian.costea@nxp.com> @@ -617,6 +617,28 @@ i2c2: i2c@401ec000 { status = "disabled"; }; + adc0: adc@401f8000 { + compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc"; + reg = <0x401f8000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x41>; + dmas = <&edma0 0 32>; + dma-names = "rx"; + vref = <1800>; + status = "disabled"; + }; + + adc1: adc@402e8000 { + compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc"; + reg = <0x402e8000 0x1000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x41>; + dmas = <&edma1 1 32>; + dma-names = "rx"; + vref = <1800>; + status = "disabled"; + }; + swt4: watchdog@40200000 { compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; reg = <0x40200000 0x1000>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3 2026-05-13 14:29 ` [PATCH 1/1] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3 Khristine Andreea Barbulescu @ 2026-05-14 5:42 ` sashiko-bot 0 siblings, 0 replies; 3+ messages in thread From: sashiko-bot @ 2026-05-14 5:42 UTC (permalink / raw) To: Khristine Andreea Barbulescu Cc: imx, robh, devicetree, Frank.Li, krzk+dt, conor+dt Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [Low] The 'vref' property included in the 'adc0' and 'adc1' nodes violates the devicetree binding schema for 'nxp,s32g2-sar-adc' and will cause 'make dtbs_check' failures. - [Low] The 'adc1: adc@402e8000' node is placed out of order by unit address in both 's32g2.dtsi' and 's32g3.dtsi'. -- commit 7673e90a3952520a499f13a94f36f7b0fd2320e8 Author: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com> arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3 This commit adds ADC0 and ADC1 nodes for S32G2 and S32G3 SoCs. > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi [ ... ] > @@ -554,6 +554,28 @@ i2c2: i2c@401ec000 { > status = "disabled"; > }; > > + adc0: adc@401f8000 { > + compatible = "nxp,s32g2-sar-adc"; > + reg = <0x401f8000 0x1000>; > + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 0x41>; > + dmas = <&edma0 0 32>; > + dma-names = "rx"; > + vref = <1800>; Does the vref property violate the nxp,s32g2-sar-adc devicetree binding schema? The schema sets additionalProperties to false and does not define a vref property, which will cause make dtbs_check failures. The standard practice is to use a vref-supply phandle rather than a raw integer value. > + status = "disabled"; > + }; > + > + adc1: adc@402e8000 { > + compatible = "nxp,s32g2-sar-adc"; > + reg = <0x402e8000 0x1000>; > + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 0x41>; > + dmas = <&edma1 1 32>; > + dma-names = "rx"; > + vref = <1800>; > + status = "disabled"; > + }; > + > swt4: watchdog@40200000 { Should the adc1 node be placed after the swt4 node to maintain ascending unit address sorting? 0x402e8000 is greater than 0x40200000. > diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi > --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi [ ... ] > @@ -617,6 +617,28 @@ i2c2: i2c@401ec000 { > status = "disabled"; > }; > > + adc0: adc@401f8000 { > + compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc"; > + reg = <0x401f8000 0x1000>; > + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 0x41>; > + dmas = <&edma0 0 32>; > + dma-names = "rx"; > + vref = <1800>; Is this vref property intended? Similar to the s32g2.dtsi file, this will trigger schema validation errors. > + status = "disabled"; > + }; > + > + adc1: adc@402e8000 { > + compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc"; > + reg = <0x402e8000 0x1000>; > + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks 0x41>; > + dmas = <&edma1 1 32>; > + dma-names = "rx"; > + vref = <1800>; > + status = "disabled"; > + }; > + > swt4: watchdog@40200000 { Does this adc1 node placement also violate ascending unit address sorting rules here in s32g3.dtsi? -- Sashiko AI review · https://sashiko.dev/#/patchset/20260513142948.640057-2-khristineandreea.barbulescu@oss.nxp.com?part=1 ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-05-14 5:42 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-05-13 14:29 [PATCH 0/1] add SAR ADC DTS support for S32G2/S32G3 SoCs Khristine Andreea Barbulescu 2026-05-13 14:29 ` [PATCH 1/1] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3 Khristine Andreea Barbulescu 2026-05-14 5:42 ` sashiko-bot
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