Re: [PATCH v2 1/1] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] ADC1 is incorrectly configured to use `edma1` instead of `edma0`, breaking DMA routing.
--

commit 3b1b0b80a34f00191fc6241e0894c052fd88edf8
Author: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>

arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3

This commit adds ADC0 and ADC1 node definitions for the S32G2 and S32G3 SoCs.

> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 51d00dac12deb..6f1952fbbcfee 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi

[ ... ]

> @@ -717,6 +727,16 @@ i2c4: i2c@402dc000 {
>  			status = "disabled";
>  		};
>  
> +		adc1: adc@402e8000 {
> +			compatible = "nxp,s32g2-sar-adc";
> +			reg = <0x402e8000 0x1000>;
> +			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 0x41>;
> +			dmas = <&edma1 1 32>;

Is it possible this should be routing to edma0 instead of edma1?

It appears that other peripherals in the 0x402xxxxx memory range use DMAMUX 1
on the edma0 controller (e.g. <&edma0 1 ...>). Since the hardware DMA request
lines for ADC1 are wired to the first eDMA controller's multiplexer, assigning
it to edma1 could result in silent DMA failures and timeouts during ADC1
operations.

> +			dma-names = "rx";
> +			status = "disabled";
> +		};
> +
>  		usdhc0: mmc@402f0000 {
>  			compatible = "nxp,s32g2-usdhc";
>  			reg = <0x402f0000 0x1000>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index e314f3c7d61d0..5cfb37c1216a7 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi

[ ... ]

> @@ -792,6 +802,16 @@ i2c4: i2c@402dc000 {
>  			status = "disabled";
>  		};
>  
> +		adc1: adc@402e8000 {
> +			compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
> +			reg = <0x402e8000 0x1000>;
> +			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 0x41>;
> +			dmas = <&edma1 1 32>;

Does this have the same eDMA controller routing regression as adc1 in
s32g2.dtsi above?

> +			dma-names = "rx";
> +			status = "disabled";
> +		};
> +
>  		usdhc0: mmc@402f0000 {
>  			compatible = "nxp,s32g3-usdhc",
>  				     "nxp,s32g2-usdhc";

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260514082639.1181240-2-khristineandreea.barbulescu@oss.nxp.com?part=1