* [PATCH v2 0/1] add SAR ADC DTS support for S32G2/S32G3 SoCs
@ 2026-05-14 8:26 Khristine Andreea Barbulescu
2026-05-14 8:26 ` [PATCH v2 1/1] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3 Khristine Andreea Barbulescu
0 siblings, 1 reply; 3+ messages in thread
From: Khristine Andreea Barbulescu @ 2026-05-14 8:26 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Frank Li,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo
This patchset aims to add one change to the S32G2/S32G3 dtsi support:
- Add SAR ADC dts support for S32G SoC based boards
v2 -> v1:
- drop 'vref' property from ADC nodes
- reorder 'adc1' node to maintain ascending
unit address order
Khristine Andreea Barbulescu (1):
arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3
arch/arm64/boot/dts/freescale/s32g2.dtsi | 22 +++++++++++++++++++++-
arch/arm64/boot/dts/freescale/s32g3.dtsi | 22 +++++++++++++++++++++-
2 files changed, 42 insertions(+), 2 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v2 1/1] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3
2026-05-14 8:26 [PATCH v2 0/1] add SAR ADC DTS support for S32G2/S32G3 SoCs Khristine Andreea Barbulescu
@ 2026-05-14 8:26 ` Khristine Andreea Barbulescu
2026-05-14 17:03 ` sashiko-bot
0 siblings, 1 reply; 3+ messages in thread
From: Khristine Andreea Barbulescu @ 2026-05-14 8:26 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Frank Li,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo
Add ADC0 and ADC1 for S32G2 and S32G3 SoCs.
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 22 +++++++++++++++++++++-
arch/arm64/boot/dts/freescale/s32g3.dtsi | 22 +++++++++++++++++++++-
2 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 51d00dac12de..6f1952fbbcfe 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,7 +3,7 @@
* NXP S32G2 SoC family
*
* Copyright (c) 2021 SUSE LLC
- * Copyright 2017-2021, 2024-2025 NXP
+ * Copyright 2017-2021, 2024-2026 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -554,6 +554,16 @@ i2c2: i2c@401ec000 {
status = "disabled";
};
+ adc0: adc@401f8000 {
+ compatible = "nxp,s32g2-sar-adc";
+ reg = <0x401f8000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 0x41>;
+ dmas = <&edma0 0 32>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
swt4: watchdog@40200000 {
compatible = "nxp,s32g2-swt";
reg = <0x40200000 0x1000>;
@@ -717,6 +727,16 @@ i2c4: i2c@402dc000 {
status = "disabled";
};
+ adc1: adc@402e8000 {
+ compatible = "nxp,s32g2-sar-adc";
+ reg = <0x402e8000 0x1000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 0x41>;
+ dmas = <&edma1 1 32>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g2-usdhc";
reg = <0x402f0000 0x1000>;
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index e314f3c7d61d..5cfb37c1216a 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright 2021-2025 NXP
+ * Copyright 2021-2026 NXP
*
* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* Ciprian Costea <ciprianmarian.costea@nxp.com>
@@ -617,6 +617,16 @@ i2c2: i2c@401ec000 {
status = "disabled";
};
+ adc0: adc@401f8000 {
+ compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
+ reg = <0x401f8000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 0x41>;
+ dmas = <&edma0 0 32>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
swt4: watchdog@40200000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40200000 0x1000>;
@@ -792,6 +802,16 @@ i2c4: i2c@402dc000 {
status = "disabled";
};
+ adc1: adc@402e8000 {
+ compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
+ reg = <0x402e8000 0x1000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 0x41>;
+ dmas = <&edma1 1 32>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g3-usdhc",
"nxp,s32g2-usdhc";
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2 1/1] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3
2026-05-14 8:26 ` [PATCH v2 1/1] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3 Khristine Andreea Barbulescu
@ 2026-05-14 17:03 ` sashiko-bot
0 siblings, 0 replies; 3+ messages in thread
From: sashiko-bot @ 2026-05-14 17:03 UTC (permalink / raw)
To: Khristine Andreea Barbulescu
Cc: Frank.Li, devicetree, robh, krzk+dt, conor+dt, imx
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] ADC1 is incorrectly configured to use `edma1` instead of `edma0`, breaking DMA routing.
--
commit 3b1b0b80a34f00191fc6241e0894c052fd88edf8
Author: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3
This commit adds ADC0 and ADC1 node definitions for the S32G2 and S32G3 SoCs.
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 51d00dac12deb..6f1952fbbcfee 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
[ ... ]
> @@ -717,6 +727,16 @@ i2c4: i2c@402dc000 {
> status = "disabled";
> };
>
> + adc1: adc@402e8000 {
> + compatible = "nxp,s32g2-sar-adc";
> + reg = <0x402e8000 0x1000>;
> + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 0x41>;
> + dmas = <&edma1 1 32>;
Is it possible this should be routing to edma0 instead of edma1?
It appears that other peripherals in the 0x402xxxxx memory range use DMAMUX 1
on the edma0 controller (e.g. <&edma0 1 ...>). Since the hardware DMA request
lines for ADC1 are wired to the first eDMA controller's multiplexer, assigning
it to edma1 could result in silent DMA failures and timeouts during ADC1
operations.
> + dma-names = "rx";
> + status = "disabled";
> + };
> +
> usdhc0: mmc@402f0000 {
> compatible = "nxp,s32g2-usdhc";
> reg = <0x402f0000 0x1000>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index e314f3c7d61d0..5cfb37c1216a7 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
[ ... ]
> @@ -792,6 +802,16 @@ i2c4: i2c@402dc000 {
> status = "disabled";
> };
>
> + adc1: adc@402e8000 {
> + compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
> + reg = <0x402e8000 0x1000>;
> + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 0x41>;
> + dmas = <&edma1 1 32>;
Does this have the same eDMA controller routing regression as adc1 in
s32g2.dtsi above?
> + dma-names = "rx";
> + status = "disabled";
> + };
> +
> usdhc0: mmc@402f0000 {
> compatible = "nxp,s32g3-usdhc",
> "nxp,s32g2-usdhc";
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260514082639.1181240-2-khristineandreea.barbulescu@oss.nxp.com?part=1
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-05-14 17:03 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-14 8:26 [PATCH v2 0/1] add SAR ADC DTS support for S32G2/S32G3 SoCs Khristine Andreea Barbulescu
2026-05-14 8:26 ` [PATCH v2 1/1] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3 Khristine Andreea Barbulescu
2026-05-14 17:03 ` sashiko-bot
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox