[PATCH 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC

[PATCH 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

This series enables the SMMU and adds DMA coherency support for the
XGMAC nodes across the affected board device trees.

Patch 1 enables the SMMU for the SoCFPGA board device trees where it
was missing. The SoC uses a different memory-mapped base address for
its peripherals, which requires the SMMU to be active so that the
Secure Device Manager (SDM) can correctly access those regions through
address translation.

Patch 2 adds the dma-coherent property to the XGMAC nodes. The SMMU
is enabled and transactions going through it are cache coherent.
Adding dma-coherent prevents redundant cache flush/invalidate
operations and potential stale data issues.

Nazim Amirul (2):
  arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees
  arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

 arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts         | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts         | 5 +++++
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts    | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts    | 5 +++++
 5 files changed, 13 insertions(+)

-- 
2.43.7

[PATCH 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

Enable the SMMU on the SoCFPGA board device trees where it was
missing. The SoC uses a different memory-mapped base address for
its peripherals, which requires the System Memory Management Unit
(SMMU) to be active so that the Secure Device Manager (SDM) can
correctly access those regions through address translation.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts      | 4 ++++
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index dae0db9f8819..66fc3c546b66 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -109,6 +109,10 @@ &usb0 {
 	disable-over-current;
 };
 
+&smmu {
+	status = "okay";
+};
+
 &watchdog0 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
index 21faa47681fa..33e6455ead0f 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
@@ -104,6 +104,10 @@ &uart0 {
 	status = "okay";
 };
 
+&smmu {
+	status = "okay";
+};
+
 &watchdog0 {
 	status = "okay";
 };
-- 
2.43.7

Re: [PATCH 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The SMMU is enabled at the board level rather than the SoC level, despite being an SoC-wide mandatory component.
--

commit b23c4db1700b818372c3d30cde1aa1e0dc267d27
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

This commit enables the System Memory Management Unit (SMMU) on several
Agilex5 SoCFPGA board device trees to allow the Secure Device Manager to
correctly access peripherals.

>     Enable the SMMU on the SoCFPGA board device trees where it was
>     missing. The SoC uses a different memory-mapped base address for
>     its peripherals, which requires the System Memory Management Unit
>     (SMMU) to be active so that the Secure Device Manager (SDM) can
>     correctly access those regions through address translation.

Since the commit message indicates the SMMU is an inherent architectural
requirement of the Agilex5 SoC itself, should the SMMU be enabled by default
in the base socfpga_agilex5.dtsi file?

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> index 262bb3e8e5c72..bdb608bb30ea6 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> @@ -107,6 +107,10 @@ &usb0 {
>  	disable-over-current;
>  };
>  
> +&smmu {
> +	status = "okay";
> +};
> +

Scattering the status = "okay" override across multiple board dts files
might not be necessary if the SMMU only relies on SoC-internal resources and
does not require board-specific configuration. Would it be better to remove
status = "disabled" from the smmu node in the base dtsi instead?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260514114111.10574-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=1

[PATCH 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

The SMMU is enabled and transactions going through it are cache
coherent. Add the dma-coherent property to the XGMAC nodes to prevent
redundant cache flush/invalidate operations and potential stale data
issues.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts         | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts         | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts    | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts    | 1 +
 5 files changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
index 25e17df0cbdb..2061d301126e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
@@ -52,6 +52,7 @@ &gmac2 {
 	phy-mode = "rgmii-id";
 	phy-handle = <&emac2_phy0>;
 	max-frame-size = <9000>;
+	dma-coherent;
 
 	mdio0 {
 		compatible = "snps,dwmac-mdio";
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 66fc3c546b66..0af0b2e7d867 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -47,6 +47,7 @@ &gmac2 {
 	phy-mode = "rgmii-id";
 	phy-handle = <&emac2_phy0>;
 	max-frame-size = <9000>;
+	dma-coherent;
 
 	mdio0 {
 		#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
index 86137380df04..9bff6b57f19d 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
@@ -46,6 +46,7 @@ &gmac2 {
 	phy-mode = "rgmii-id";
 	phy-handle = <&emac2_phy0>;
 	max-frame-size = <9000>;
+	dma-coherent;
 
 	mdio0 {
 		#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
index e728cedb4cbd..6c61add0ef09 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
@@ -49,6 +49,7 @@ &gmac2 {
 	phy-mode = "rgmii-id";
 	phy-handle = <&emac2_phy0>;
 	max-frame-size = <9000>;
+	dma-coherent;
 
 	mdio0 {
 		compatible = "snps,dwmac-mdio";
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
index 33e6455ead0f..1a9d44e2bcb3 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
@@ -44,6 +44,7 @@ &gmac0 {
 	phy-mode = "rgmii-id";
 	phy-handle = <&emac0_phy0>;
 	max-frame-size = <9000>;
+	dma-coherent;
 
 	mdio0 {
 		#address-cells = <1>;
-- 
2.43.7

Re: [PATCH 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Critical] Other SMMU-attached DMA masters in the base SoC `.dtsi` lack the `dma-coherent` property, risking data corruption.
- [High] The `dma-coherent` property is applied at the board `.dts` level instead of the SoC `.dtsi` level, leaving `gmac1` unprotected.
--

commit 3e00440f9beb8b27250cd5096c497340a958ee43
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

arm64: dts: socfpga: Add dma-coherent to XGMAC nodes

This commit adds the dma-coherent property to XGMAC nodes in various
Agilex3 and Agilex5 board files. The commit message notes that transactions
going through the enabled SMMU are cache coherent, and this property prevents
redundant cache operations.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> index bdb608bb30ea6..dd878547c3056 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> @@ -45,6 +45,7 @@ &gmac2 {
>  	phy-mode = "rgmii-id";
>  	phy-handle = <&emac2_phy0>;
>  	max-frame-size = <9000>;
> +	dma-coherent;

Should this hardware integration property be added directly to the base
socfpga_agilex5.dtsi file instead of the individual board files?

By adding it at the board level, it appears gmac1 (which is defined in
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi) is missed. If a future board
enables gmac1, it will silently lack this property, which could cause explicit
arm64 cache invalidations to discard dma writes and result in stale data.

Also, the commit message mentions that transactions going through the SMMU
are cache coherent. Does this mean other SMMU-attached devices in the
base socfpga_agilex5.dtsi also need this property?

For example, looking at arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi,
several other components are routed through the SMMU but lack dma-coherent:

		usb0: usb@10b00000 {
			...
			iommus = <&smmu 6>;
		};

		dmac0: dma-controller@0 {
			...
			iommus = <&smmu 8>;
		};

If these physically coherent devices are mapped as non-coherent, the kernel
will issue explicit cache invalidations (like dc ivac during dma_unmap_single
for device-to-memory transfers).

Because a coherent device writes directly into the CPU cache, this post-dma
kernel cache invalidation will discard the newly written data. Could this
cause silent regressions with active data corruption for devices like usb
storage or dma controllers?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260514114111.10574-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=2