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From: Conor Dooley <conor.dooley@microchip.com>
To: Jia Wang <wangjia@ultrarisc.com>
Cc: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Linus Walleij <linusw@kernel.org>,
	Bartosz Golaszewski <brgl@kernel.org>,
	Samuel Holland <samuel.holland@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Conor Dooley <conor@kernel.org>, <devicetree@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-gpio@vger.kernel.org>
Subject: Re: [PATCH 0/9] riscv: ultrarisc: add DP1000 SoC DT and pinctrl support
Date: Fri, 15 May 2026 11:05:40 +0100	[thread overview]
Message-ID: <20260515-brink-dealer-d0610c0dbc7b@wendy> (raw)
In-Reply-To: <20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com>

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Hey,

On Fri, May 15, 2026 at 09:17:56AM +0800, Jia Wang wrote:
> This series adds initial Devicetree support for the UltraRISC DP1000 RISC-V
> SoC and two DP1000-based boards (Milk-V Titan and Rongda M0).
> 
> The series introduces the required DT bindings, adds the DP1000 pinctrl
> driver, and provides the initial SoC/board DTS files.
> 
> Notes:
>   - Clocks are configured and enabled by firmware before Linux boots. Linux
>     does not manage clock rates or gating at runtime on this platform.
>     Therefore the initial DT only models the fixed clocks required by
>     standard drivers, and no clock controller/driver is provided.

I really disagree with this approach. In my experience it never ends up
working out and ends up being disruptive, because it is either an over
simplification of the clock tree and condenses multiple different clocks
into one where rates are similar or because firmware changes mean clock
rate changes down the line. I would much rather you modelled the clocks
accurately, even if that just means that a read-only clock controller is
implemented. Alternatively, if firmware does all of your clock control,
you can implement this using rpmi/mpoxy using clk-rpmi.c

>   - The DP1000 pinctrl binding supports two child node styles under the same
>     controller compatible:
>       * legacy DP1000-specific nodes using phandle-array properties
>         "pinctrl-pins" and "pinconf-pins"
>       * generic pinctrl nodes using "pins", "function" and generic pin
>         configuration properties
>     The legacy form is kept for compatibility with existing vendor DTs.

Why would we want "legacy" stuff in mainline when this is a brand new
platform? "legacy" vendor devicetrees are not something that mainline
cares about, sorry.

Additionally, these pinctrl patches should be sent standalone to the
pinctrl maintainers, they're likely to go through lots of revisions and
a different maintainer applies them.

>   - The bindings for "ultrarisc,dp1000-uart" and "ultrarisc,dp1000-pcie" are
>     being reviewed in separate series, since the DP1000 SoC DTS introduced
>     here uses those compatibles:
>     * Link: https://lore.kernel.org/lkml/20260429-ultrarisc-serial-v7-3-e475cce9e274@ultrarisc.com/
>     * Link: https://lore.kernel.org/lkml/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com/
>   - ARCH_ULTRARISC support is being reviewed separately:
>     * Link: https://lore.kernel.org/lkml/20260427-ultrarisc-pcie-v4-1-98935f6cdfb5@ultrarisc.com/

IMO, this patch needs to be in this series so that it compiles.

Cheers,
Conor.

> 
> Testing:
>   - dt_binding_check and yamllint (all new/modified binding YAMLs)
>   - dtbs_check and dtbs (RISC-V, including dp1000-milkv-titan.dtb and
>     dp1000-rongda-m0.dtb)
>   - Kernel build for RISC-V and boot-tested on DP1000 (Milk-V Titan and
>     Rongda M0)
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> ---
> Jia Wang (9):
>       dt-bindings: vendor-prefixes: add Rongda
>       dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible
>       dt-bindings: riscv: Add UltraRISC DP1000 bindings
>       dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl bindings
>       riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000
>       pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver
>       riscv: dts: ultrarisc: add Rongda M0 board device tree
>       riscv: dts: ultrarisc: add Milk-V Titan board device tree
>       riscv: defconfig: enable ARCH_ULTRARISC
> 
>  .../bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml | 168 ++++
>  Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
>  .../devicetree/bindings/riscv/ultrarisc.yaml       |  27 +
>  .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
>  MAINTAINERS                                        |  15 +
>  arch/riscv/boot/dts/Makefile                       |   1 +
>  arch/riscv/boot/dts/ultrarisc/Makefile             |   3 +
>  .../dts/ultrarisc/dp1000-milkv-titan-pinctrl.dtsi  | 107 +++
>  .../boot/dts/ultrarisc/dp1000-milkv-titan.dts      | 182 +++++
>  .../dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi    |  85 ++
>  arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts | 111 +++
>  arch/riscv/boot/dts/ultrarisc/dp1000.dtsi          | 851 +++++++++++++++++++++
>  arch/riscv/configs/defconfig                       |   1 +
>  drivers/pinctrl/Kconfig                            |   1 +
>  drivers/pinctrl/Makefile                           |   1 +
>  drivers/pinctrl/ultrarisc/Kconfig                  |  23 +
>  drivers/pinctrl/ultrarisc/Makefile                 |   4 +
>  drivers/pinctrl/ultrarisc/pinctrl-dp1000.c         | 112 +++
>  drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c      | 746 ++++++++++++++++++
>  drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h      |  71 ++
>  .../dt-bindings/pinctrl/ultrarisc,dp1000-pinctrl.h |  65 ++
>  21 files changed, 2577 insertions(+)
> ---
> base-commit: 50897c955902c93ae71c38698abb910525ebdc89
> change-id: 20260316-ultrarisc-pinctrl-efa6e24c4803
> 
> Best regards,
> --  
> Jia Wang <wangjia@ultrarisc.com>
> 

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      parent reply	other threads:[~2026-05-15 10:06 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-15  1:17 [PATCH 0/9] riscv: ultrarisc: add DP1000 SoC DT and pinctrl support Jia Wang via B4 Relay
2026-05-15  1:17 ` [PATCH 1/9] dt-bindings: vendor-prefixes: add Rongda Jia Wang via B4 Relay
2026-05-15  1:20   ` sashiko-bot
2026-05-15  1:25     ` Jia Wang
2026-05-15  1:17 ` [PATCH 2/9] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Jia Wang via B4 Relay
2026-05-15 10:06   ` Conor Dooley
2026-05-15  1:17 ` [PATCH 3/9] dt-bindings: riscv: Add UltraRISC DP1000 bindings Jia Wang via B4 Relay
2026-05-15 10:08   ` Conor Dooley
2026-05-15  1:18 ` [PATCH 4/9] dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl bindings Jia Wang via B4 Relay
2026-05-15  1:49   ` sashiko-bot
2026-05-15  8:43     ` Jia Wang
2026-05-15 10:12   ` Conor Dooley
2026-05-15  1:18 ` [PATCH 5/9] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Jia Wang via B4 Relay
2026-05-15  2:02   ` sashiko-bot
2026-05-15 10:26   ` Conor Dooley
2026-05-15  1:18 ` [PATCH 6/9] pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver Jia Wang via B4 Relay
2026-05-15  2:28   ` sashiko-bot
2026-05-15  1:18 ` [PATCH 7/9] riscv: dts: ultrarisc: add Rongda M0 board device tree Jia Wang via B4 Relay
2026-05-15  2:37   ` sashiko-bot
2026-05-15 10:28   ` Conor Dooley
2026-05-15  1:18 ` [PATCH 8/9] riscv: dts: ultrarisc: add Milk-V Titan " Jia Wang via B4 Relay
2026-05-15  2:50   ` sashiko-bot
2026-05-15  1:18 ` [PATCH 9/9] riscv: defconfig: enable ARCH_ULTRARISC Jia Wang via B4 Relay
2026-05-15  2:59   ` sashiko-bot
2026-05-15 10:05 ` Conor Dooley [this message]

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