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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Jian Hu <jian.hu@amlogic.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
	 Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	 Neil Armstrong <neil.armstrong@linaro.org>,
	Jerome Brunet <jbrunet@baylibre.com>,
	 Xianwei Zhao <xianwei.zhao@amlogic.com>,
	Kevin Hilman <khilman@baylibre.com>,
	 Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	 devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
	 linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 02/10] dt-bindings: clock: Add Amlogic A9 PLL clock controller
Date: Fri, 15 May 2026 10:09:03 +0200	[thread overview]
Message-ID: <20260515-subtle-sepia-tuatara-cfee3d@quoll> (raw)
In-Reply-To: <20260511-b4-a9_clk-v1-2-41cb4071b7c9@amlogic.com>

On Mon, May 11, 2026 at 08:47:24PM +0800, Jian Hu wrote:
> Add the PLL clock controller dt-bindings for the Amlogic A9 SoC family.
> 
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
>  .../bindings/clock/amlogic,a9-pll-clkc.yaml        | 110 +++++++++++++++++++++
>  include/dt-bindings/clock/amlogic,a9-pll-clkc.h    |  55 +++++++++++
>  2 files changed, 165 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml
> new file mode 100644
> index 000000000000..4ee6013ba1a1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml
> @@ -0,0 +1,110 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2026 Amlogic, Inc. All rights reserved
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/amlogic,a9-pll-clkc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Amlogic A9 Series PLL Clock Controller
> +
> +maintainers:
> +  - Neil Armstrong <neil.armstrong@linaro.org>
> +  - Jerome Brunet <jbrunet@baylibre.com>
> +  - Jian Hu <jian.hu@amlogic.com>
> +  - Xianwei Zhao <xianwei.zhao@amlogic.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - amlogic,a9-gp0-pll
> +      - amlogic,a9-hifi0-pll
> +      - amlogic,a9-hifi1-pll
> +      - amlogic,a9-mclk0-pll
> +      - amlogic,a9-mclk1-pll
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +
> +  clocks:
> +    items:
> +      - description: pll input oscillator gate
> +      - description: fixed input clock source for mclk_sel_0
> +      - description: u3p2pll input clock source for mclk_sel_0 (optional)

Second clock is also optional. Drop "(optional)" comment, just
confusing.

> +    minItems: 1
> +
> +  clock-names:
> +    items:
> +      - const: in0
> +      - const: in1
> +      - const: in2

Pretty pointless names, drop property.

> +    minItems: 1
> +
> +required:
> +  - compatible
> +  - '#clock-cells'
> +  - reg
> +  - clocks
> +  - clock-names
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - amlogic,a9-mclk0-pll
> +              - amlogic,a9-mclk1-pll
> +
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 3

No, minItems instead. maxItems is already 3, so what is the point of
redefining it?

> +
> +        clock-names:
> +          maxItems: 3
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - amlogic,a9-gp0-pll
> +              - amlogic,a9-hifi0-pll
> +              - amlogic,a9-hifi1-pll
> +
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 1
> +
> +        clock-names:
> +          maxItems: 1
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    apb4 {

soc

> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        clock-controller@8200 {
> +            compatible = "amlogic,a9-gp0-pll";
> +            reg = <0x0 0x8200 0x0 0x20>;
> +            #clock-cells = <1>;
> +            clocks = <&scmi_clk 0>;
> +            clock-names = "in0";
> +        };
> +
> +        clock-controller@8330 {
> +            compatible = "amlogic,a9-mclk0-pll";
> +            reg = <0x0 0x8330 0x0 0x14>;
> +            #clock-cells = <1>;
> +            clocks = <&scmi_clk 4>,
> +                     <&scmi_clk 8>;
> +            clock-names = "in0", "in1";

One example is enough, you have exactly the same properties.


Best regards,
Krzysztof


  parent reply	other threads:[~2026-05-15  8:09 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-11 12:47 [PATCH 00/10] Add support for A9 family clock controller Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 01/10] dt-bindings: clock: Add Amlogic A9 SCMI " Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 02/10] dt-bindings: clock: Add Amlogic A9 PLL " Jian Hu via B4 Relay
2026-05-12  4:18   ` sashiko-bot
2026-05-15  8:09   ` Krzysztof Kozlowski [this message]
2026-05-11 12:47 ` [PATCH 03/10] dt-bindings: clock: Add Amlogic A9 peripherals " Jian Hu via B4 Relay
2026-05-14 16:15   ` Jerome Brunet
2026-05-15  8:10   ` Krzysztof Kozlowski
2026-05-11 12:47 ` [PATCH 04/10] dt-bindings: clock: Add Amlogic A9 AO " Jian Hu via B4 Relay
2026-05-15  8:10   ` Krzysztof Kozlowski
2026-05-11 12:47 ` [PATCH 05/10] clk: amlogic: PLL l_detect signal supports active-high configuration Jian Hu via B4 Relay
2026-05-11 15:47   ` Brian Masney
2026-05-14 15:13   ` Jerome Brunet
2026-05-11 12:47 ` [PATCH 06/10] clk: amlogic: PLL reset signal supports active-low configuration Jian Hu via B4 Relay
2026-05-11 15:21   ` Brian Masney
2026-05-13  3:53     ` Jian Hu
2026-05-12  4:48   ` sashiko-bot
2026-05-14 15:16   ` Jerome Brunet
2026-05-11 12:47 ` [PATCH 07/10] clk: amlogic: Support POWER_OF_TWO for PLL pre-divider Jian Hu via B4 Relay
2026-05-11 15:23   ` Brian Masney
2026-05-14 15:11   ` Jerome Brunet
2026-05-11 12:47 ` [PATCH 08/10] clk: amlogic: Add A9 PLL clock controller driver Jian Hu via B4 Relay
2026-05-11 15:36   ` Brian Masney
2026-05-13  7:25     ` Jian Hu
2026-05-12  5:56   ` sashiko-bot
2026-05-14 16:12   ` Jerome Brunet
2026-05-11 12:47 ` [PATCH 09/10] clk: amlogic: Add A9 peripherals " Jian Hu via B4 Relay
2026-05-11 15:42   ` Brian Masney
2026-05-13  8:50     ` Jian Hu
2026-05-12  6:18   ` sashiko-bot
2026-05-11 12:47 ` [PATCH 10/10] clk: amlogic: Add A9 AO " Jian Hu via B4 Relay
2026-05-11 15:45   ` Brian Masney
2026-05-13  9:19     ` Jian Hu
2026-05-12 20:47   ` sashiko-bot
2026-05-14 16:27   ` Jerome Brunet

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