From: sashiko-bot@kernel.org
To: "Dmitry Baryshkov" <dmitry.baryshkov@oss.qualcomm.com>
Cc: krzk+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org,
conor+dt@kernel.org
Subject: Re: [PATCH v7 3/6] arm64: dts: qcom: sc8280xp: Add Iris core
Date: Fri, 15 May 2026 11:42:07 +0000 [thread overview]
Message-ID: <20260515114207.B877AC2BCB0@smtp.kernel.org> (raw)
In-Reply-To: <20260515-iris-sc8280xp-v7-3-2e21f6db1897@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The `iris` device tree node adds an `mmcx` power domain and two `required-opps` per OPP entry, which violates the fallback compatible's DT binding schema and causes hardware instability due to unhandled power domain scaling.
--
commit 39fd9222ebc24cef337abe30cd891e4af77696e1
Author: Konrad Dybcio <konradybcio@kernel.org>
arm64: dts: qcom: sc8280xp: Add Iris core
Add the required nodes to enable Iris core on SC8280XP.
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 41c57e7dc4333..45e1dd5a230cd 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
[ ... ]
> @@ -4181,6 +4189,97 @@ usb_1_dwc3_ss: endpoint {
> };
> };
>
> + iris: video-codec@aa00000 {
> + compatible = "qcom,sc8280xp-iris", "qcom,sm8250-venus";
> + reg = <0x0 0x0aa00000 0x0 0x100000>;
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
[ ... ]
> + power-domains = <&videocc MVS0C_GDSC>,
> + <&videocc MVS0_GDSC>,
> + <&rpmhpd SC8280XP_MX>,
> + <&rpmhpd SC8280XP_MMCX>;
> + power-domain-names = "venus",
> + "vcodec0",
> + "mx",
> + "mmcx";
The qcom,sm8250-venus fallback compatible is used here. Does the
qcom,sm8250-venus.yaml device tree binding schema support a fourth power
domain?
It appears the schema might restrict power-domains to a maximum of 3 items
(venus, vcodec0, mx), which could trigger dtbs_check failures when mmcx
is added.
[ ... ]
> + iris_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-240000000 {
> + opp-hz = /bits/ 64 <240000000>;
> + required-opps = <&rpmhpd_opp_svs>,
> + <&rpmhpd_opp_low_svs>;
> + };
[ ... ]
> + opp-560000000 {
> + opp-hz = /bits/ 64 <560000000>;
> + required-opps = <&rpmhpd_opp_nom>,
> + <&rpmhpd_opp_turbo_l1>;
> + };
> + };
> + };
When using the qcom,sm8250-venus fallback, the Venus driver currently
configures a single OPP PM domain (mx) via dev_pm_opp_set_config().
Since this node specifies two required-opps per state, will the generic OPP
core skip scaling the mmcx rail? When _set_required_opps() in
drivers/opp/core.c iterates over expected devices, a missing mmcx device
pointer might cause the mmcx rail to remain trapped at the static low_svs
level voted by the videocc node.
If the Venus hardware operates at turbo frequencies (e.g., 560MHz) while mmcx
remains at low_svs, can this undervolt the hardware and cause system
instability?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260515-iris-sc8280xp-v7-0-2e21f6db1897@oss.qualcomm.com?part=3
next prev parent reply other threads:[~2026-05-15 11:42 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-15 10:56 [PATCH v7 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
2026-05-15 10:56 ` [PATCH v7 1/6] media: dt-bindings: Document SC8280XP/SM8350 Iris Dmitry Baryshkov
2026-05-15 10:56 ` [PATCH v7 2/6] arm64: dts: qcom: sc8280xp: sort reserved memory regions Dmitry Baryshkov
2026-05-15 10:56 ` [PATCH v7 3/6] arm64: dts: qcom: sc8280xp: Add Iris core Dmitry Baryshkov
2026-05-15 11:42 ` sashiko-bot [this message]
2026-05-15 12:14 ` Dmitry Baryshkov
2026-05-15 10:56 ` [PATCH v7 4/6] arm64: dts: qcom: sc8280xp-x13s: Enable Iris Dmitry Baryshkov
2026-05-15 10:56 ` [PATCH v7 5/6] arm64: dts: qcom: sm8350: add Iris device Dmitry Baryshkov
2026-05-15 12:08 ` sashiko-bot
2026-05-15 10:56 ` [PATCH v7 6/6] arm64: dts: qcom: sm8350-hdk: enable Iris core Dmitry Baryshkov
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