[PATCH v2 0/1] add PIT DTS support for S32G2/S32G3 SoCs

[PATCH v2 0/1] add PIT DTS support for S32G2/S32G3 SoCs

[Khristine Andreea Barbulescu]

This patchset aims to add one change to the S32G2/S32G3 dtsi support:
- Add PIT dts support for S32G SoC based boards

v2 -> v1:
- Drop the redundant PIT example from the binding

Khristine Andreea Barbulescu (1):
  arm64: dts: s32g: add PIT support for s32g2 and s32g3

 arch/arm64/boot/dts/freescale/s32g2.dtsi | 20 +++++++++++++++++++-
 arch/arm64/boot/dts/freescale/s32g3.dtsi | 20 +++++++++++++++++++-
 2 files changed, 38 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH v2 1/1] arm64: dts: s32g: add PIT support for s32g2 and s32g3

[Khristine Andreea Barbulescu]

Add PIT0 and PIT1 for S32G2 and S32G3 SoCs

Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi | 20 +++++++++++++++++++-
 arch/arm64/boot/dts/freescale/s32g3.dtsi | 20 +++++++++++++++++++-
 2 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 51d00dac12de..57ff97e44507 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,7 +3,7 @@
  * NXP S32G2 SoC family
  *
  * Copyright (c) 2021 SUSE LLC
- * Copyright 2017-2021, 2024-2025 NXP
+ * Copyright 2017-2021, 2024-2026 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -417,6 +417,15 @@ edma0: dma-controller@40144000 {
 			clock-names = "dmamux0", "dmamux1";
 		};
 
+		pit0: pit@40188000 {
+			compatible = "nxp,s32g2-pit";
+			reg = <0x40188000 0x3000>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 61>;
+			clock-names = "pit";
+			status = "disabled";
+		};
+
 		can0: can@401b4000 {
 			compatible = "nxp,s32g2-flexcan";
 			reg = <0x401b4000 0xa000>;
@@ -622,6 +631,15 @@ edma1: dma-controller@40244000 {
 			clock-names = "dmamux0", "dmamux1";
 		};
 
+		pit1: pit@40288000 {
+			compatible = "nxp,s32g2-pit";
+			reg = <0x40288000 0x3000>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 61>;
+			clock-names = "pit";
+			status = "disabled";
+		};
+
 		can2: can@402a8000 {
 			compatible = "nxp,s32g2-flexcan";
 			reg = <0x402a8000 0xa000>;
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index e314f3c7d61d..efe5398e1240 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
- * Copyright 2021-2025 NXP
+ * Copyright 2021-2026 NXP
  *
  * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
  *          Ciprian Costea <ciprianmarian.costea@nxp.com>
@@ -475,6 +475,15 @@ edma0: dma-controller@40144000 {
 			clock-names = "dmamux0", "dmamux1";
 		};
 
+		pit0: pit@40188000 {
+			compatible = "nxp,s32g3-pit", "nxp,s32g2-pit";
+			reg = <0x40188000 0x3000>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 61>;
+			clock-names = "pit";
+			status = "disabled";
+		};
+
 		can0: can@401b4000 {
 			compatible = "nxp,s32g3-flexcan",
 					   "nxp,s32g2-flexcan";
@@ -693,6 +702,15 @@ edma1: dma-controller@40244000 {
 			clock-names = "dmamux0", "dmamux1";
 		};
 
+		pit1: pit@40288000 {
+			compatible = "nxp,s32g3-pit", "nxp,s32g2-pit";
+			reg = <0x40288000 0x3000>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 61>;
+			clock-names = "pit";
+			status = "disabled";
+		};
+
 		can2: can@402a8000 {
 			compatible = "nxp,s32g3-flexcan",
 					   "nxp,s32g2-flexcan";
-- 
2.34.1

Re: [PATCH v2 1/1] arm64: dts: s32g: add PIT support for s32g2 and s32g3

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The newly added device tree nodes `pit0` and `pit1` are named `pit@...` instead of the generic name `timer@...`.
--

commit 296fdf97d8d5f42b2426eda4d41b0132d74ccbbd
Author: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>

arm64: dts: s32g: add PIT support for s32g2 and s32g3

This commit adds device tree nodes for the Periodic Interrupt Timer (PIT0 and
PIT1) blocks on the NXP S32G2 and S32G3 SoCs.

> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 51d00dac12deb..57ff97e445075 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
[ ... ]
> @@ -417,6 +417,15 @@ edma0: dma-controller@40144000 {
>  			clock-names = "dmamux0", "dmamux1";
>  		};
>  
> +		pit0: pit@40188000 {

This isn't a bug, but should these nodes use the generic name timer instead of
pit? The Devicetree Specification recommends using generic names that reflect
the primary function of the device rather than specific IP block acronyms.

> +			compatible = "nxp,s32g2-pit";
> +			reg = <0x40188000 0x3000>;
> +			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 61>;
> +			clock-names = "pit";
> +			status = "disabled";
> +		};
> +
[ ... ]
> @@ -622,6 +631,15 @@ edma1: dma-controller@40244000 {
>  			clock-names = "dmamux0", "dmamux1";
>  		};
>  
> +		pit1: pit@40288000 {

Could this node also be named timer@40288000 for the same reason?

> +			compatible = "nxp,s32g2-pit";
> +			reg = <0x40288000 0x3000>;
> +			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 61>;
> +			clock-names = "pit";
> +			status = "disabled";
> +		};
[ ... ]
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index e314f3c7d61d0..efe5398e12403 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
[ ... ]
> @@ -475,6 +475,15 @@ edma0: dma-controller@40144000 {
>  			clock-names = "dmamux0", "dmamux1";
>  		};
>  
> +		pit0: pit@40188000 {

And similarly, could this node be updated to timer@40188000?

> +			compatible = "nxp,s32g3-pit", "nxp,s32g2-pit";
> +			reg = <0x40188000 0x3000>;
> +			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 61>;
> +			clock-names = "pit";
> +			status = "disabled";
> +		};
> +
[ ... ]
> @@ -693,6 +702,15 @@ edma1: dma-controller@40244000 {
>  			clock-names = "dmamux0", "dmamux1";
>  		};
>  
> +		pit1: pit@40288000 {

And timer@40288000 here?

> +			compatible = "nxp,s32g3-pit", "nxp,s32g2-pit";
> +			reg = <0x40288000 0x3000>;
> +			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 61>;
> +			clock-names = "pit";
> +			status = "disabled";
> +		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260518063547.2890353-2-khristineandreea.barbulescu@oss.nxp.com?part=1