Re: [PATCH v9 5/9] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `dphy` node is missing the required `interrupts` property and a SoC-specific compatible string.
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commit ceae1b5da24380c4a30d9a8b480a23eaee3c0814
Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support

This commit adds MIPI CSI-2 support to the Allwinner V3s SoC. It introduces
the device tree nodes for the CSI0 controller, the MIPI CSI-2 bridge, and
the D-PHY block.

> diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
[ ... ]
> +		dphy: d-phy@1cb2000 {
> +			compatible = "allwinner,sun6i-a31-mipi-dphy";

Should a SoC-specific compatible string like "allwinner,sun8i-v3s-mipi-dphy"
be included here alongside the generic a31 fallback?

> +			reg = <0x01cb2000 0x1000>;
> +			clocks = <&ccu CLK_BUS_CSI>,
> +				 <&ccu CLK_MIPI_CSI>;
> +			clock-names = "bus", "mod";
> +			resets = <&ccu RST_BUS_CSI>;

Will this node fail dtbs_check schema validation? The existing device tree
binding schema for "allwinner,sun6i-a31-mipi-dphy" requires an interrupts
property, which appears to be missing here.

If the V3s hardware physically lacks a D-PHY interrupt, would it be better
to add the V3s-specific compatible string and update the binding schema
to make the interrupts property conditionally optional for the V3s?

> +			allwinner,direction = "rx";
> +			status = "disabled";
> +			#phy-cells = <0>;
> +		};
> +

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Sashiko AI review · https://sashiko.dev/#/patchset/20260518153339.619947-1-paulk@sys-base.io?part=5