[PATCH v6] arm64: dts: imx95: Correct PCIe outbound address space configuration

[PATCH v6] arm64: dts: imx95: Correct PCIe outbound address space configuration

[Richard Zhu]

Fix the PCIe outbound memory ranges for both pcie0 and pcie1
controllers on i.MX95.

The memory window size was incorrectly set to 256MB during initial
bring-up, but the hardware supports up to 4GB of outbound address space
per controller. Expand the memory region from 256MB (0x10000000) to
~3840MB (0xf0000000), starting at the base of each controller's
assigned CPU address range (0x9_00000000 for pcie0, 0xa_00000000 for
pcie1).

Additionally, ECAM cannot be mapped as I/O space. Use a memory region
to map the I/O space instead, and relocate the 1MB I/O region to
immediately follow the memory region at offset 0xf0000000 within each
window.

Fixes: 3b1d5deb29ff ("arm64: dts: imx95: add pcie[0,1] and pcie-ep[0,1] support")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx95.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
---
Changes in v6:
- Set the PCI I/O bus address starting at 0x0000_0000, while keeping the
CPU-side mapping at 0x9_f000_0000.

Changes in v5:
- Expand the outbound address space from 256MB to 3840MB, starting at the
base of each controller's assigned CPU address range.
- Use a memory region to map the I/O space.

Changes in v4:
Update the flag from 0x82000000 to 0x83000000 to declare a 64-bit PCI space.

Changes in v3:
Update the commit message, and set the region size to the max hardware-supported memory space 4G.

Changes in v2:
Add the Fixes tag, and rebase to latest imx/dt64 branch.

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index adcc0e1d3696..18eeb6286db7 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1939,8 +1939,8 @@ pcie0: pcie@4c300000 {
 			      <0 0x4c360000 0 0x10000>,
 			      <0 0x4c340000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
-			ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
-				 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
+			ranges = <0x82000000 0x0 0x00000000 0x9 0x00000000 0x0 0xf0000000>,
+				 <0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -2014,8 +2014,8 @@ pcie1: pcie@4c380000 {
 			      <0 0x4c3e0000 0 0x10000>,
 			      <0 0x4c3c0000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
-			ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
-				 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
+			ranges = <0x82000000 0x0 0x00000000 0xa 0x00000000 0x0 0xf0000000>,
+				 <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-- 
2.37.1

Re: [PATCH v6] arm64: dts: imx95: Correct PCIe outbound address space configuration

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Expanding the 32-bit PCIe outbound memory window to cover 3.84GB (from 0x00000000 to 0xefffffff) intercepts and blackholes inbound 32-bit DMA transactions, breaking device DMA.
--

commit d83be49665e8cce20876ad202979b5eb76f6a536
Author: Richard Zhu <hongxing.zhu@nxp.com>

arm64: dts: imx95: Correct PCIe outbound address space configuration

This commit expands the PCIe outbound memory ranges from 256MB to ~3840MB
for both pcie0 and pcie1 controllers on i.MX95. It also relocates the 1MB
I/O region to offset 0xf0000000 within each window.

> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 71394871d8dd0..074f8865eb2d3 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1852,8 +1852,8 @@ pcie0: pcie@4c300000 {
>  			      <0 0x4c360000 0 0x10000>,
>  			      <0 0x4c340000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
> -			ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
> -				 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
> +			ranges = <0x82000000 0x0 0x00000000 0x9 0x00000000 0x0 0xf0000000>,
> +				 <0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>;

Will mapping this 3.84GB window into the 32-bit PCI address space intercept
inbound 32-bit DMA transactions?

Because this uses the 0x82000000 flag (32-bit memory space), it covers the
PCI address range from 0x00000000 to 0xEFFFFFFF. A Root Port will typically
not forward memory requests from the PCIe link to the system bus if the
target address falls within its programmed downstream memory base and limit.

This means inbound DMA from a PCIe endpoint using an address in this 3.84GB
range might be treated as a peer-to-peer transaction and dropped or routed
downstream, failing to reach system memory.

If the IOMMU is enabled, the PCI core will reserve this 3.84GB window in the
IOMMU allocator to prevent overlap. Will this leave only 256MB of 32-bit IOVA
space available, potentially exhausting it and breaking drivers with 32-bit
DMA masks?

Could this outbound window either be kept small, or mapped into the 64-bit PCI
address space (using the 0x83000000 flag) at an address above 4GB to preserve
the 32-bit PCI address space for inbound DMA?

[ ... ]

> @@ -1927,8 +1927,8 @@ pcie1: pcie@4c380000 {
>  			      <0 0x4c3e0000 0 0x10000>,
>  			      <0 0x4c3c0000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
> -			ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
> -				 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
> +			ranges = <0x82000000 0x0 0x00000000 0xa 0x00000000 0x0 0xf0000000>,
> +				 <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;

Does the same 32-bit DMA mapping limitation apply to this pcie1 configuration
as well?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260519070223.361106-1-hongxing.zhu@nxp.com?part=1