* [PATCH v2 0/1] add USB PHY node and USB OTG pinctrl support to S32G2/S32G3 SoCs
@ 2026-05-20 15:10 Khristine Andreea Barbulescu
2026-05-20 15:10 ` [PATCH v2 1/1] arm64: dts: Add usbphynop and usbotg pinctrl for S32G platforms Khristine Andreea Barbulescu
0 siblings, 1 reply; 4+ messages in thread
From: Khristine Andreea Barbulescu @ 2026-05-20 15:10 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Frank Li,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo
This patchset aims to add two changes to the S32G2/S32G3 dtsi support:
- Add the usbphynop node for S32G SoC based boards
- Add the usbotg pinctrl support for S32G SoC based boards
v2 -> v1:
- use hyphenated naming for USB OTG pin groups
- replace deprecated 'fsl,usbphy' with 'phys'
- move 'usbphynop' node to the SoC-level dtsi
Khristine Andreea Barbulescu (1):
arm64: dts: Add usbphynop and usbotg pinctrl for S32G platforms
arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 ++-
arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 ++-
.../boot/dts/freescale/s32gxxxa-evb.dtsi | 46 ++++++++++++++++++-
.../boot/dts/freescale/s32gxxxa-rdb.dtsi | 46 ++++++++++++++++++-
4 files changed, 102 insertions(+), 4 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2 1/1] arm64: dts: Add usbphynop and usbotg pinctrl for S32G platforms
2026-05-20 15:10 [PATCH v2 0/1] add USB PHY node and USB OTG pinctrl support to S32G2/S32G3 SoCs Khristine Andreea Barbulescu
@ 2026-05-20 15:10 ` Khristine Andreea Barbulescu
2026-05-20 15:27 ` sashiko-bot
2026-05-21 15:40 ` Enric Balletbo i Serra
0 siblings, 2 replies; 4+ messages in thread
From: Khristine Andreea Barbulescu @ 2026-05-20 15:10 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Frank Li,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo
Add the usbphynop node and the usbotg pinctrl
support for the S32G2 and S32G3 SoCs.
This enables the USB controller to reference the
generic PHY and use the required pinmux for USB OTG ops.
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 ++-
arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 ++-
.../boot/dts/freescale/s32gxxxa-evb.dtsi | 46 ++++++++++++++++++-
.../boot/dts/freescale/s32gxxxa-rdb.dtsi | 46 ++++++++++++++++++-
4 files changed, 102 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 51d00dac12de..a35bb284270e 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,7 +3,7 @@
* NXP S32G2 SoC family
*
* Copyright (c) 2021 SUSE LLC
- * Copyright 2017-2021, 2024-2025 NXP
+ * Copyright 2017-2021, 2024-2026 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -108,6 +108,11 @@ psci {
};
};
+ usbphynop: usbphynop {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index e314f3c7d61d..b980e5f2b059 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright 2021-2025 NXP
+ * Copyright 2021-2026 NXP
*
* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* Ciprian Costea <ciprianmarian.costea@nxp.com>
@@ -165,6 +165,11 @@ scmi_shmem: shm@d0000000 {
};
};
+ usbphynop: usbphynop {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
index 803ff4531077..26009c1e90dc 100644
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright 2024 NXP
+ * Copyright 2024, 2026 NXP
*
* Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
* Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
@@ -245,6 +245,39 @@ dspi5-grp4 {
bias-pull-up;
};
};
+
+ usbotg_pins: usbotg-pins {
+ usbotg-grp0 {
+ pinmux = <0x3802>, <0x3812>,
+ <0x3822>, <0x3832>,
+ <0x3842>, <0x3852>,
+ <0x3862>, <0x3872>,
+ <0x37f2>, <0x3882>,
+ <0x3892>;
+ };
+
+ usbotg-grp1 {
+ pinmux = <0x3e1>, <0x3f1>,
+ <0x401>, <0x411>,
+ <0xbc1>, <0xbd1>,
+ <0xbe1>, <0x701>;
+ output-enable;
+ input-enable;
+ slew-rate = <208>;
+ };
+
+ usbotg-grp2 {
+ pinmux = <0xb80>, <0xb90>, <0xbb0>;
+ input-enable;
+ slew-rate = <208>;
+ };
+
+ usbotg-grp3 {
+ pinmux = <0xba1>;
+ output-enable;
+ slew-rate = <208>;
+ };
+ };
};
&can0 {
@@ -304,3 +337,14 @@ &spi5 {
pinctrl-names = "default";
status = "okay";
};
+
+&usbmisc {
+ status = "okay";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbotg_pins>;
+ phys = <&usbphynop>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
index 979868f6d2c5..a8abb10b0e7a 100644
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright 2024 NXP
+ * Copyright 2024, 2026 NXP
*
* Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
* Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
@@ -199,6 +199,39 @@ dspi5-grp4 {
bias-pull-up;
};
};
+
+ usbotg_pins: usbotg-pins {
+ usbotg-grp0 {
+ pinmux = <0x3802>, <0x3812>,
+ <0x3822>, <0x3832>,
+ <0x3842>, <0x3852>,
+ <0x3862>, <0x3872>,
+ <0x37f2>, <0x3882>,
+ <0x3892>;
+ };
+
+ usbotg-grp1 {
+ pinmux = <0x3e1>, <0x3f1>,
+ <0x401>, <0x411>,
+ <0xbc1>, <0xbd1>,
+ <0xbe1>, <0x701>;
+ output-enable;
+ input-enable;
+ slew-rate = <208>;
+ };
+
+ usbotg-grp2 {
+ pinmux = <0xb80>, <0xb90>, <0xbb0>;
+ input-enable;
+ slew-rate = <208>;
+ };
+
+ usbotg-grp3 {
+ pinmux = <0xba1>;
+ output-enable;
+ slew-rate = <208>;
+ };
+ };
};
&can0 {
@@ -257,3 +290,14 @@ &i2c4 {
pinctrl-1 = <&i2c4_gpio_pins>;
status = "okay";
};
+
+&usbmisc {
+ status = "okay";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbotg_pins>;
+ phys = <&usbphynop>;
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2 1/1] arm64: dts: Add usbphynop and usbotg pinctrl for S32G platforms
2026-05-20 15:10 ` [PATCH v2 1/1] arm64: dts: Add usbphynop and usbotg pinctrl for S32G platforms Khristine Andreea Barbulescu
@ 2026-05-20 15:27 ` sashiko-bot
2026-05-21 15:40 ` Enric Balletbo i Serra
1 sibling, 0 replies; 4+ messages in thread
From: sashiko-bot @ 2026-05-20 15:27 UTC (permalink / raw)
To: Khristine Andreea Barbulescu; +Cc: imx, devicetree, robh, Frank.Li, conor+dt
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The USB PHY node uses a non-generic name 'usbphynop' which violates Devicetree naming conventions.
- [Low] Explicitly setting 'status = "okay";' for the 'usbmisc' node in the board files is redundant.
--
commit 9f52e7dedd0f8d5b7d9ec5b0f3215fe2bb1c921b
Author: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
arm64: dts: Add usbphynop and usbotg pinctrl for S32G platforms
This commit adds the generic USB PHY node and USB OTG pinmux configurations
for the S32G2 and S32G3 SoCs. It enables the USB controller to reference the
generic PHY and use the required pins for USB OTG operations.
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 51d00dac12deb..a35bb284270ed 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
[ ... ]
> @@ -108,6 +108,11 @@ psci {
> };
> };
>
> + usbphynop: usbphynop {
[Severity: Low]
This isn't a bug, but does this node name align with the Devicetree
Specification?
The Devicetree Specification (Section 2.2.2 'Generic Names Recommendation')
states that a node's name should be generic and reflect the function of the
device, rather than its precise programming model or driver name.
Could this be named something more generic like 'phy' or 'usb-phy'
instead of 'usbphynop'?
> + compatible = "usb-nop-xceiv";
> + #phy-cells = <0>;
> + };
> +
> soc@0 {
[ ... ]
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index e314f3c7d61d0..b980e5f2b059c 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
[ ... ]
> @@ -165,6 +165,11 @@ scmi_shmem: shm@d0000000 {
> };
> };
>
> + usbphynop: usbphynop {
[Severity: Low]
This isn't a bug, but does this node name align with the Devicetree
Specification?
The Devicetree Specification (Section 2.2.2 'Generic Names Recommendation')
states that a node's name should be generic and reflect the function of the
device, rather than its precise programming model or driver name.
Could this be named something more generic like 'phy' or 'usb-phy'
instead of 'usbphynop'?
> + compatible = "usb-nop-xceiv";
> + #phy-cells = <0>;
> + };
> +
> soc@0 {
[ ... ]
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> index 803ff45310771..26009c1e90dcf 100644
> --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
[ ... ]
> @@ -304,3 +337,14 @@ &spi5 {
> pinctrl-names = "default";
> status = "okay";
> };
> +
> +&usbmisc {
> + status = "okay";
> +};
[Severity: Low]
This isn't a bug, but is it necessary to explicitly set the status for the
usbmisc node here?
In the base SoC devicetrees (s32g2.dtsi and s32g3.dtsi), the usbmisc node
is defined without a 'status = "disabled";' property.
Since nodes default to an 'okay' status when the status property is omitted,
could this assignment be redundant?
> +
> +&usbotg {
[ ... ]
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> index 979868f6d2c5c..a8abb10b0e7ae 100644
> --- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
[ ... ]
> @@ -257,3 +290,14 @@ &i2c4 {
> pinctrl-1 = <&i2c4_gpio_pins>;
> status = "okay";
> };
> +
> +&usbmisc {
> + status = "okay";
> +};
[Severity: Low]
This isn't a bug, but is it necessary to explicitly set the status for the
usbmisc node here?
In the base SoC devicetrees (s32g2.dtsi and s32g3.dtsi), the usbmisc node
is defined without a 'status = "disabled";' property.
Since nodes default to an 'okay' status when the status property is omitted,
could this assignment be redundant?
> +
> +&usbotg {
> + pinctrl-names = "default";
> + pinctrl-0 = <&usbotg_pins>;
> + phys = <&usbphynop>;
> + status = "okay";
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260520151007.4193688-2-khristineandreea.barbulescu@oss.nxp.com?part=1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 1/1] arm64: dts: Add usbphynop and usbotg pinctrl for S32G platforms
2026-05-20 15:10 ` [PATCH v2 1/1] arm64: dts: Add usbphynop and usbotg pinctrl for S32G platforms Khristine Andreea Barbulescu
2026-05-20 15:27 ` sashiko-bot
@ 2026-05-21 15:40 ` Enric Balletbo i Serra
1 sibling, 0 replies; 4+ messages in thread
From: Enric Balletbo i Serra @ 2026-05-21 15:40 UTC (permalink / raw)
To: Khristine Andreea Barbulescu
Cc: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Frank Li,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Pengutronix Kernel Team, linux-arm-kernel, imx,
devicetree, linux-kernel, NXP S32 Linux, Christophe Lizzi,
Alberto Ruiz
Hi Khristine,
Thank you to apply my reviews.
On Wed, May 20, 2026 at 5:10 PM Khristine Andreea Barbulescu
<khristineandreea.barbulescu@oss.nxp.com> wrote:
>
> Add the usbphynop node and the usbotg pinctrl
> support for the S32G2 and S32G3 SoCs.
>
> This enables the USB controller to reference the
> generic PHY and use the required pinmux for USB OTG ops.
>
I tried testing the patches, but unfortunately, they didn't work for
me on top of the current mainline. Any idea what could be wrong?
[ 40.019850] usb_phy_generic usbphynop: dummy supplies not allowed
for exclusive requests (id=vbus)
[ 40.268467] imx_usb 44064000.usb: No over current polarity defined
[ 40.293272] ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
[ 40.308834] ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
[ 40.309475] usb usb1: New USB device found, idVendor=1d6b,
idProduct=0002, bcdDevice= 7.01
[ 40.309485] usb usb1: New USB device strings: Mfr=3, Product=2,
SerialNumber=1
[ 40.309492] usb usb1: Product: EHCI Host Controller
[ 40.309498] usb usb1: Manufacturer: Linux 7.1.0-rc4+ ehci_hcd
[ 40.309503] usb usb1: SerialNumber: ci_hdrc.0
[ 40.311051] hub 1-0:1.0: USB hub found
[ 40.748830] usb 1-1: new high-speed USB device number 2 using ci_hdrc
[ 46.038582] usb 1-1: new full-speed USB device number 3 using ci_hdrc
[ 61.347813] usb 1-1: device descriptor read/64, error -110
[ 76.707030] usb 1-1: device descriptor read/64, error -110
[ 76.817100] usb usb1-port1: attempt power cycle
[ 77.256992] usb 1-1: new full-speed USB device number 4 using ci_hdrc
[ 87.826466] usb 1-1: device not accepting address 4, error -110
[ 87.956454] usb 1-1: new full-speed USB device number 5 using ci_hdrc
[ 98.545933] usb 1-1: device not accepting address 5, error -110
[ 98.546070] usb usb1-port1: unable to enumerate USB device
It looks like a problem with the ULPI communication because I cannot
read the ULPI registers.
Thanks,
Enric
> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 ++-
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 ++-
> .../boot/dts/freescale/s32gxxxa-evb.dtsi | 46 ++++++++++++++++++-
> .../boot/dts/freescale/s32gxxxa-rdb.dtsi | 46 ++++++++++++++++++-
> 4 files changed, 102 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 51d00dac12de..a35bb284270e 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -3,7 +3,7 @@
> * NXP S32G2 SoC family
> *
> * Copyright (c) 2021 SUSE LLC
> - * Copyright 2017-2021, 2024-2025 NXP
> + * Copyright 2017-2021, 2024-2026 NXP
> */
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -108,6 +108,11 @@ psci {
> };
> };
>
> + usbphynop: usbphynop {
> + compatible = "usb-nop-xceiv";
> + #phy-cells = <0>;
> + };
> +
> soc@0 {
> compatible = "simple-bus";
> #address-cells = <1>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index e314f3c7d61d..b980e5f2b059 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> /*
> - * Copyright 2021-2025 NXP
> + * Copyright 2021-2026 NXP
> *
> * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> * Ciprian Costea <ciprianmarian.costea@nxp.com>
> @@ -165,6 +165,11 @@ scmi_shmem: shm@d0000000 {
> };
> };
>
> + usbphynop: usbphynop {
> + compatible = "usb-nop-xceiv";
> + #phy-cells = <0>;
> + };
> +
> soc@0 {
> compatible = "simple-bus";
> #address-cells = <1>;
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> index 803ff4531077..26009c1e90dc 100644
> --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> /*
> - * Copyright 2024 NXP
> + * Copyright 2024, 2026 NXP
> *
> * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
> @@ -245,6 +245,39 @@ dspi5-grp4 {
> bias-pull-up;
> };
> };
> +
> + usbotg_pins: usbotg-pins {
> + usbotg-grp0 {
> + pinmux = <0x3802>, <0x3812>,
> + <0x3822>, <0x3832>,
> + <0x3842>, <0x3852>,
> + <0x3862>, <0x3872>,
> + <0x37f2>, <0x3882>,
> + <0x3892>;
> + };
> +
> + usbotg-grp1 {
> + pinmux = <0x3e1>, <0x3f1>,
> + <0x401>, <0x411>,
> + <0xbc1>, <0xbd1>,
> + <0xbe1>, <0x701>;
> + output-enable;
> + input-enable;
> + slew-rate = <208>;
> + };
> +
> + usbotg-grp2 {
> + pinmux = <0xb80>, <0xb90>, <0xbb0>;
> + input-enable;
> + slew-rate = <208>;
> + };
> +
> + usbotg-grp3 {
> + pinmux = <0xba1>;
> + output-enable;
> + slew-rate = <208>;
> + };
> + };
> };
>
> &can0 {
> @@ -304,3 +337,14 @@ &spi5 {
> pinctrl-names = "default";
> status = "okay";
> };
> +
> +&usbmisc {
> + status = "okay";
> +};
> +
> +&usbotg {
> + pinctrl-names = "default";
> + pinctrl-0 = <&usbotg_pins>;
> + phys = <&usbphynop>;
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> index 979868f6d2c5..a8abb10b0e7a 100644
> --- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> /*
> - * Copyright 2024 NXP
> + * Copyright 2024, 2026 NXP
> *
> * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
> @@ -199,6 +199,39 @@ dspi5-grp4 {
> bias-pull-up;
> };
> };
> +
> + usbotg_pins: usbotg-pins {
> + usbotg-grp0 {
> + pinmux = <0x3802>, <0x3812>,
> + <0x3822>, <0x3832>,
> + <0x3842>, <0x3852>,
> + <0x3862>, <0x3872>,
> + <0x37f2>, <0x3882>,
> + <0x3892>;
> + };
> +
> + usbotg-grp1 {
> + pinmux = <0x3e1>, <0x3f1>,
> + <0x401>, <0x411>,
> + <0xbc1>, <0xbd1>,
> + <0xbe1>, <0x701>;
> + output-enable;
> + input-enable;
> + slew-rate = <208>;
> + };
> +
> + usbotg-grp2 {
> + pinmux = <0xb80>, <0xb90>, <0xbb0>;
> + input-enable;
> + slew-rate = <208>;
> + };
> +
> + usbotg-grp3 {
> + pinmux = <0xba1>;
> + output-enable;
> + slew-rate = <208>;
> + };
> + };
> };
>
> &can0 {
> @@ -257,3 +290,14 @@ &i2c4 {
> pinctrl-1 = <&i2c4_gpio_pins>;
> status = "okay";
> };
> +
> +&usbmisc {
> + status = "okay";
> +};
> +
> +&usbotg {
> + pinctrl-names = "default";
> + pinctrl-0 = <&usbotg_pins>;
> + phys = <&usbphynop>;
> + status = "okay";
> +};
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2026-05-21 15:41 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-20 15:10 [PATCH v2 0/1] add USB PHY node and USB OTG pinctrl support to S32G2/S32G3 SoCs Khristine Andreea Barbulescu
2026-05-20 15:10 ` [PATCH v2 1/1] arm64: dts: Add usbphynop and usbotg pinctrl for S32G platforms Khristine Andreea Barbulescu
2026-05-20 15:27 ` sashiko-bot
2026-05-21 15:40 ` Enric Balletbo i Serra
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