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From: sashiko-bot@kernel.org
To: "Richard Zhu" <hongxing.zhu@nxp.com>
Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
	imx@lists.linux.dev, Frank.Li@kernel.org, robh@kernel.org,
	conor+dt@kernel.org
Subject: Re: [PATCH v5 1/3] dt-bindings: imx6q-pcie: Add optional interrupt entries for intr, aer and pme
Date: Thu, 21 May 2026 09:54:05 +0000	[thread overview]
Message-ID: <20260521095405.A5EFD1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260521093255.61585-2-hongxing.zhu@nxp.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Expanding the global `interrupts` and `interrupt-names` properties without adding conditional blocks allows legacy compatibles to incorrectly pass validation with unsupported interrupts.
- [Medium] Using an ordered list for `items` fails validation if a device omits the optional intermediate `dma` interrupt but includes subsequent interrupts.
--

commit be2769e2cb772d7043d8c01877a0a7fecb468b12
Author: Richard Zhu <hongxing.zhu@nxp.com>

dt-bindings: imx6q-pcie: Add optional interrupt entries for intr, aer and pme

This commit adds three new dedicated hardware interrupt lines (intr, aer, pme)
introduced in the i.MX95 PCIe controller. These interrupts are added to the
global interrupts property as optional entries to maintain compatibility with
older SoC variants.

> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index 9d1349855b422..cf709132ff1e2 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -58,12 +58,18 @@ properties:
>      items:
>        - description: builtin MSI controller.
>        - description: builtin DMA controller.
> +      - description: PCIe event interrupt.
> +      - description: builtin AER SPI standalone interrupt line.
> +      - description: builtin PME SPI standalone interrupt line.

[Severity: Medium]
Will this expansion allow legacy compatibles to incorrectly pass validation
with unsupported interrupts?

The commit message notes that earlier i.MX PCIe variants lack these
dedicated hardware interrupt lines. Without adding an if-then conditional
block to restrict interrupts and interrupt-names to maxItems: 2 for older
variants, invalid device trees specifying these unsupported interrupts will
now silently pass validation.

>  
>    interrupt-names:
>      minItems: 1
>      items:
>        - const: msi
>        - const: dma
> +      - const: intr
> +      - const: aer
> +      - const: pme

[Severity: Medium]
Does using an ordered list for items cause validation to fail if a device
omits the optional dma interrupt?

In YAML schema validation, an items list enforces strict positional matching.
If a device tree defines msi, intr, aer, and pme but omits the optional dma
interrupt, the intr string will appear at index 1 and fail the strict
evaluation against "- const: dma".

Could the schema use an unordered list (such as oneOf or items: enum: [...])
to allow independently optional interrupts without strict sequencing errors?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260521093255.61585-1-hongxing.zhu@nxp.com?part=1

  reply	other threads:[~2026-05-21  9:54 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-21  9:32 [PATCH v5 0/3] Add root port reset to support link recovery Richard Zhu
2026-05-21  9:32 ` [PATCH v5 1/3] dt-bindings: imx6q-pcie: Add optional interrupt entries for intr, aer and pme Richard Zhu
2026-05-21  9:54   ` sashiko-bot [this message]
2026-05-21  9:32 ` [PATCH v5 2/3] arm64: dts: imx95: Add dma, intr, aer and pme interrupts for PCIe Richard Zhu
2026-05-21 10:27   ` sashiko-bot
2026-05-21  9:32 ` [PATCH v5 3/3] PCI: imx6: Add root port reset to support link recovery Richard Zhu
2026-05-21 11:21   ` sashiko-bot
2026-05-22  2:41     ` Hongxing Zhu

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