Re: [PATCH 3/3] arm64: dts: renesas: rzt2h-n2h-evk: Enable xSPI nodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The 'spi-max-frequency' property is missing from the SPI NOR flash peripheral nodes (flash@0) under both xspi0 and xspi1.
- [Low] The unit addresses in the partition node names for xspi0 do not match their corresponding 'reg' base addresses.
--

commit 61aa7aa9a0a6654d6fbf30169801908b8247d8cd
Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

arm64: dts: renesas: rzt2h-n2h-evk: Enable xSPI nodes

Enable the xSPI0 and xSPI1 controllers on the RZ/T2H N2H EVK board.

> diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> index f87c2492f414a..fff63d08e3a3c 100644
> --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi

[ ... ]

> @@ -395,3 +451,86 @@ &wdt2 {
>  	timeout-sec = <60>;
>  };
>  
> +&xspi0 {
> +	pinctrl-0 = <&xspi0_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +
> +	assigned-clocks = <&cpg CPG_CORE R9A09G077_XSPI_CLK0>;
> +	assigned-clock-rates = <50000000>;
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;

[Severity: Medium]
Should there be a 'spi-max-frequency' property specified here?

Standard SPI peripheral Device Tree bindings require the 'spi-max-frequency'
property on child nodes to explicitly specify the maximum SPI clock speed
the device can tolerate. Omitting this property will cause 'dtbs_check'
warnings.

Furthermore, without it, the SPI core framework initializes the device's
max_speed_hz to 0, forcing reliance on the controller's internal clock
fallback behavior.

> +		m25p,fast-read;

[ ... ]

> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "bl2-0";
> +				reg = <0x00000000 0x00060000>;
> +				read-only;
> +			};
> +
> +			partition@1fb000 {
> +				label = "fip-0";
> +				reg = <0x00060000 0x007a0000>;

[Severity: Low]
Does this unit address match the first address specified in its 'reg' property?

The Device Tree specification requires the unit-address (the part after '@') in
a node name to exactly match the first address specified in its 'reg'
property. Here, 'partition@1fb000' defines its base address as '0x00060000'.

This mismatch will trigger 'unit_address_vs_reg' warnings during device tree
compilation.

> +				read-only;
> +			};
> +
> +			partition@300000 {
> +				label = "user-0";
> +				reg = <0x800000 0x003800000>;

[Severity: Low]
Does this unit address match the first address specified in its 'reg' property?

The Device Tree specification requires the unit-address (the part after '@') in
a node name to exactly match the first address specified in its 'reg'
property. Here, 'partition@300000' defines its base address as '0x800000'.

This mismatch will trigger 'unit_address_vs_reg' warnings during device tree
compilation.

Additionally, does the size value '0x003800000' contain an extraneous leading
zero?

> +			};
> +		};
> +	};
> +};
> +
> +&xspi1 {
> +	pinctrl-0 = <&xspi1_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +
> +	assigned-clocks = <&cpg CPG_CORE R9A09G077_XSPI_CLK1>;
> +	assigned-clock-rates = <50000000>;
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;

[Severity: Medium]
Should there be a 'spi-max-frequency' property specified here?

Standard SPI peripheral Device Tree bindings require the 'spi-max-frequency'
property on child nodes to explicitly specify the maximum SPI clock speed
the device can tolerate. Omitting this property will cause 'dtbs_check'
warnings.

Furthermore, without it, the SPI core framework initializes the device's
max_speed_hz to 0, forcing reliance on the controller's internal clock
fallback behavior.

> +		m25p,fast-read;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260526204045.3481604-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=3