[PATCH] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores

[PATCH] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores

[Guodong Xu]

Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse
provides a forward progress guarantee on LR/SC sequences in main
memory regions with cacheability and coherence PMAs.

The SpacemiT X100 core supports it per the SpacemiT K3 hardware
specification.

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 arch/riscv/boot/dts/spacemit/k3.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index d4be8de8fc6cc..ccb483b439c5f 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -36,7 +36,7 @@ cpu_0: cpu@0 {
 					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
 					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
 					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
-					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
 					       "zicond", "zicsr", "zifencei", "zihintntl",
 					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
 					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@@ -77,7 +77,7 @@ cpu_1: cpu@1 {
 					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
 					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
 					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
-					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
 					       "zicond", "zicsr", "zifencei", "zihintntl",
 					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
 					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@@ -118,7 +118,7 @@ cpu_2: cpu@2 {
 					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
 					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
 					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
-					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
 					       "zicond", "zicsr", "zifencei", "zihintntl",
 					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
 					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@@ -159,7 +159,7 @@ cpu_3: cpu@3 {
 					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
 					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
 					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
-					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
 					       "zicond", "zicsr", "zifencei", "zihintntl",
 					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
 					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@@ -200,7 +200,7 @@ cpu_4: cpu@4 {
 					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
 					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
 					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
-					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
 					       "zicond", "zicsr", "zifencei", "zihintntl",
 					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
 					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@@ -241,7 +241,7 @@ cpu_5: cpu@5 {
 					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
 					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
 					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
-					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
 					       "zicond", "zicsr", "zifencei", "zihintntl",
 					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
 					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@@ -282,7 +282,7 @@ cpu_6: cpu@6 {
 					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
 					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
 					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
-					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
 					       "zicond", "zicsr", "zifencei", "zihintntl",
 					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
 					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
@@ -323,7 +323,7 @@ cpu_7: cpu@7 {
 					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
 					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
 					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
-					       "ziccamoa", "ziccif", "zicclsm", "zicntr",
+					       "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
 					       "zicond", "zicsr", "zifencei", "zihintntl",
 					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
 					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",

---
base-commit: 5d67b1f204472df70f7c7189c01fa405f3ccb503
change-id: 20260207-k3-ziccrse-b3e2d4d43aec

Best regards,
--  
Guodong Xu <guodong@riscstar.com>

Re: [PATCH] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores

[Guodong Xu]

On Tue, May 26, 2026 at 3:23 PM Guodong Xu <guodong@riscstar.com> wrote:
>
> Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse
> provides a forward progress guarantee on LR/SC sequences in main
> memory regions with cacheability and coherence PMAs.
>
> The SpacemiT X100 core supports it per the SpacemiT K3 hardware
> specification.

For the record, I have tested this change on SpacemiT K3 Pico-ITX.

The stress test is run by enabling CONFIG_LOCK_TORTURE_TEST=y then
boots the kernel with:

  locktorture.torture_type=spin_lock locktorture.nwriters_stress=16

driving all 8 harts. It survived sustained torture [ran for ~10 minutes]
with 0 Fail.

... ...
[  735.588947] torture_spin_lock_write_delay: delay = 25 jiffies.
[  738.015096] torture_spin_lock_write_delay: delay = 25 jiffies.
[  739.204713] torture_spin_lock_write_delay: delay = 25 jiffies.
[  741.195211] Writes:  Total: 714319420  Max/Min: 45946599/43679876   Fail: 0

Thanks,
Guodong / docularxu
docularxu@outlook.com

>
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
>  arch/riscv/boot/dts/spacemit/k3.dtsi | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi

Re: [PATCH] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores

[Yixun Lan]

Hi Guodong,

On 13:18 Thu 28 May     , Guodong Xu wrote:
> On Tue, May 26, 2026 at 3:23 PM Guodong Xu <guodong@riscstar.com> wrote:
> >
> > Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse
> > provides a forward progress guarantee on LR/SC sequences in main
> > memory regions with cacheability and coherence PMAs.
> >
> > The SpacemiT X100 core supports it per the SpacemiT K3 hardware
> > specification.
> 
> For the record, I have tested this change on SpacemiT K3 Pico-ITX.
> 
> The stress test is run by enabling CONFIG_LOCK_TORTURE_TEST=y then
> boots the kernel with:
> 
>   locktorture.torture_type=spin_lock locktorture.nwriters_stress=16
> 
> driving all 8 harts. It survived sustained torture [ran for ~10 minutes]
> with 0 Fail.
> 
> ... ...
> [  735.588947] torture_spin_lock_write_delay: delay = 25 jiffies.
> [  738.015096] torture_spin_lock_write_delay: delay = 25 jiffies.
> [  739.204713] torture_spin_lock_write_delay: delay = 25 jiffies.
> [  741.195211] Writes:  Total: 714319420  Max/Min: 45946599/43679876   Fail: 0
> 
I appreciate you give more info about the test, just want to make sure,
for the kernel config, the CONFIG_RISCV_TICKET_SPINLOCKS is not enabled?
so it will fall back to use ziccrse implementation..
-- 
Yixun Lan (dlan)

Re: [PATCH] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores

[Guodong Xu]

Hi, Yixun

On Fri, May 29, 2026 at 2:22 PM Yixun Lan <dlan@kernel.org> wrote:
>
> Hi Guodong,
>
> On 13:18 Thu 28 May     , Guodong Xu wrote:
> > On Tue, May 26, 2026 at 3:23 PM Guodong Xu <guodong@riscstar.com> wrote:
> > >
> > > Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse
> > > provides a forward progress guarantee on LR/SC sequences in main
> > > memory regions with cacheability and coherence PMAs.
> > >
> > > The SpacemiT X100 core supports it per the SpacemiT K3 hardware
> > > specification.
> >
> > For the record, I have tested this change on SpacemiT K3 Pico-ITX.
> >
> > The stress test is run by enabling CONFIG_LOCK_TORTURE_TEST=y then
> > boots the kernel with:
> >
> >   locktorture.torture_type=spin_lock locktorture.nwriters_stress=16
> >
> > driving all 8 harts. It survived sustained torture [ran for ~10 minutes]
> > with 0 Fail.
> >
> > ... ...
> > [  735.588947] torture_spin_lock_write_delay: delay = 25 jiffies.
> > [  738.015096] torture_spin_lock_write_delay: delay = 25 jiffies.
> > [  739.204713] torture_spin_lock_write_delay: delay = 25 jiffies.
> > [  741.195211] Writes:  Total: 714319420  Max/Min: 45946599/43679876   Fail: 0
> >
> I appreciate you give more info about the test, just want to make sure,
> for the kernel config, the CONFIG_RISCV_TICKET_SPINLOCKS is not enabled?
> so it will fall back to use ziccrse implementation..

Correct. Thanks for double-checking.

In the above test, CONFIG_RISCV_TICKET_SPINLOCKS was not enabled.
And since X100 has neither Zabha nor Zacas, the runtime selection in
riscv_spinlock_init() falls through to the Ziccrse branch.

BR,
Guodong Xu
docularxu@outlook.com

> --
> Yixun Lan (dlan)