Re: [PATCH v3 10/15] drm/tidss: Add support for DPIENABLE bit

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message claims to modify the DPIENABLE bit in `dispc_vp_enable()` and `dispc_vp_disable()`, but the code actually implements this in `dispc_vp_prepare()` and `dispc_vp_unprepare()`.
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commit 5f892829b86a9d1dabfa16f8442393394955354e
Author: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

drm/tidss: Add support for DPIENABLE bit

This commit adds support for the DPIENABLE bit in the VP_CONTROL register,
which provides power savings on the AM62L SoC when disabled. It introduces a
new feature flag to track this capability and updates the initialization
paths to disable it by default. The driver then turns the bit on and off
when DPI output is active.

> Let's add a new feature flag for this, 'has_vp_control_dpienable', and
> implement the support.  Disable DPIENABLE for all videoports at resume
> time, so that it is 0 by default. Specifically enable and disable it in
> dispc_vp_enable() and dispc_vp_disable() for DPI output.

[Severity: Medium]
Is the commit message accurate about where the bit is enabled and disabled?

The commit message states that the DPIENABLE bit is managed in
dispc_vp_enable() and dispc_vp_disable().

However, the patch actually applies these register modifications in
dispc_vp_prepare() and dispc_vp_unprepare().

Could the commit message be updated to correctly reflect the functions
modified in the implementation?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260529-beagley-ai-display-v3-0-7fefdc5d1adf@ideasonboard.com?part=10