Re: [PATCH v10 6/6] arm64: dts: s32g: describe GPIO and EIRQ resources in SIUL2 pinctrl node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The `reg` property for the `swt8` watchdog device is missing the `0x` prefix for its base address.
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commit 1403ffa829f6f3074ef410621ae401b08c310e0a
Author: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>

arm64: dts: s32g: describe GPIO and EIRQ resources in SIUL2 pinctrl node

This commit updates the SIUL2 pinctrl nodes in the s32g2 and s32g3 device
trees to describe GPIO and EIRQ registers. It adds the PGPDO, PGPDI, and
EIRQ register windows along with the corresponding controller properties.

> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi

[ ... ]

> 		swt8: watchdog@40500000 {
> 			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
> 			reg = <40500000 0x1000>;

[Severity: High]
This isn't a bug introduced by this patch, but while reviewing the s32g3
device tree changes, I noticed this pre-existing issue in the swt8 node.

Is it intentional that the reg property uses a decimal base address instead
of a hexadecimal one?

Since there is no 0x prefix, 40500000 is evaluated as decimal, which is
0x269FEC0 in hexadecimal. This does not match the intended hardware
address of 0x40500000 specified in the unit address.

If a board enables this watchdog device, could the driver attempt to
ioremap the wrong physical memory address and trigger a synchronous
external abort?

> 			clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> 			clock-names = "counter", "module", "register";
> 			status = "disabled";
> 		};

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Sashiko AI review · https://sashiko.dev/#/patchset/20260602080132.3256239-1-khristineandreea.barbulescu@oss.nxp.com?part=6