Re: [PATCH v6 1/4] dt-bindings: pci: Strictly distinguish C0 from C1-C5

[Rob Herring <robh@kernel.org>]

On Tue, Jun 02, 2026 at 01:33:23PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Instead of using the ECAM registers as the first entry, strictly make a
> distinction between C0 and C1-C5. This is needed because otherwise the
> unit address doesn't match the first "reg" entry. We also cannot change
> the ordering of these nodes to follow the ECAM addresses because that
> would put them outside of their "control bus" hierarchy since the ECAM
> address space is a global one outside of any of the control busses.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v6:
> - add maxItems as suggested by Sashiko

Sashiko was wrong here. While the analysis was correct for json schema, 
it didn't account for DT schema's processing of the schemas to the final 
json schema. In this case, this:

items:
 - {}
 - {}

is transformed to:

type: array
additionalItems: false
minItems: 2
maxItems: 2
items:
 - {}
 - {}

The reason is a fixed, defined length list is the rule, not the 
exception for DT.

Rob