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From: sashiko-bot@kernel.org
To: "Ciprian Costea" <ciprianmarian.costea@oss.nxp.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, imx@lists.linux.dev,
	conor+dt@kernel.org, Frank.Li@kernel.org
Subject: Re: [PATCH RESEND v4 5/8] can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk
Date: Wed, 03 Jun 2026 08:15:19 +0000	[thread overview]
Message-ID: <20260603081519.8EA0A1F00899@smtp.kernel.org> (raw)
In-Reply-To: <20260603071342.641874-6-ciprianmarian.costea@oss.nxp.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Concurrent lockless modification of `skb_irq_queue` leading to linked list corruption.
--

commit 5585c21d3d6c362465f049b7368b7a16b3da034f
Author: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk

This commit introduces FLEXCAN_QUIRK_IRQ_BERR to handle hardware with a
dedicated interrupt line for bus errors and device state changes. It adds
the flexcan_irq_esr() handler and enables/disables the new IRQ line as
needed.

> diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c
> index 32e4d4da00a1c..23ddf79106410 100644
> --- a/drivers/net/can/flexcan/flexcan-core.c
> +++ b/drivers/net/can/flexcan/flexcan-core.c
[ ... ]
> @@ -1912,6 +1929,13 @@ static int flexcan_open(struct net_device *dev)
>  			goto out_free_irq_boff;
>  	}
>  
> +	if (priv->devtype_data.quirks & FLEXCAN_QUIRK_IRQ_BERR) {
> +		err = request_irq(priv->irq_err,
> +				  flexcan_irq_esr, IRQF_SHARED, dev->name, dev);

[Severity: High]
This is a pre-existing issue, but this quirk continues a pattern where
separate interrupt handlers are registered on distinct physical IRQ lines.
Is there anything preventing flexcan_irq_esr() from executing concurrently
with the mailbox interrupt handler (flexcan_irq_mb) on a different CPU?

If they run concurrently, can this lead to lockless doubly-linked list
corruption?

The CAN rx_offload framework expects SKB enqueuing functions to be
serialized. However, if flexcan_irq_esr() calls flexcan_do_state() or
flexcan_do_berr() which use can_rx_offload_queue_timestamp(), it will
insert SKBs into offload->skb_irq_queue locklessly via
__skb_queue_add_sort().

At the same time, flexcan_do_mb() running from flexcan_irq_mb() can call
can_rx_offload_irq_offload_timestamp() or
can_rx_offload_get_echo_skb_queue_timestamp(), which also locklessly modify
the same skb_irq_queue.

Could this concurrent access scramble the list's next/prev pointers, leading
to kernel panics or infinite loops during NAPI processing?

> +		if (err)
> +			goto out_free_irq_boff;
> +	}
> +

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260603071342.641874-1-ciprianmarian.costea@oss.nxp.com?part=5

  reply	other threads:[~2026-06-03  8:15 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-03  7:13 [PATCH RESEND v4 0/8] can: flexcan: Add NXP S32N79 SoC support Ciprian Costea
2026-06-03  7:13 ` [PATCH RESEND v4 1/8] can: flexcan: use dedicated IRQ handlers for multi-IRQ platforms Ciprian Costea
2026-06-03  7:29   ` sashiko-bot
2026-06-03 10:06   ` Enric Balletbo i Serra
2026-06-03  7:13 ` [PATCH RESEND v4 2/8] can: flexcan: disable all IRQ lines in flexcan_chip_interrupts_enable() Ciprian Costea
2026-06-03  7:13 ` [PATCH RESEND v4 3/8] can: flexcan: split rx/tx masks per mailbox IRQ line Ciprian Costea
2026-06-03  7:49   ` sashiko-bot
2026-06-03  7:13 ` [PATCH RESEND v4 4/8] dt-bindings: can: fsl,flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-06-03  8:02   ` sashiko-bot
2026-06-03  7:13 ` [PATCH RESEND v4 5/8] can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk Ciprian Costea
2026-06-03  8:15   ` sashiko-bot [this message]
2026-06-03  7:13 ` [PATCH RESEND v4 6/8] can: flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-06-03  8:25   ` sashiko-bot
2026-06-03  7:13 ` [PATCH RESEND v4 7/8] arm64: dts: s32n79: add FlexCAN nodes Ciprian Costea
2026-06-03  7:13 ` [PATCH RESEND v4 8/8] arm64: dts: s32n79: enable FlexCAN devices Ciprian Costea
2026-06-03  9:39 ` [PATCH RESEND v4 0/8] can: flexcan: Add NXP S32N79 SoC support Bough Chen
2026-06-03 10:28   ` Enric Balletbo i Serra
2026-06-03 10:33     ` Ciprian Marian Costea
  -- strict thread matches above, loose matches on Subject: below --
2026-04-21 10:25 Ciprian Costea
2026-04-21 10:26 ` [PATCH RESEND v4 5/8] can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk Ciprian Costea

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