From: sashiko-bot@kernel.org
To: "Ciprian Costea" <ciprianmarian.costea@oss.nxp.com>
Cc: Frank.Li@kernel.org, robh@kernel.org, devicetree@vger.kernel.org,
imx@lists.linux.dev, conor+dt@kernel.org
Subject: Re: [PATCH RESEND v4 6/8] can: flexcan: add NXP S32N79 SoC support
Date: Wed, 03 Jun 2026 08:25:10 +0000 [thread overview]
Message-ID: <20260603082510.F32ED1F0089A@smtp.kernel.org> (raw)
In-Reply-To: <20260603071342.641874-7-ciprianmarian.costea@oss.nxp.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] Wakeup functionality is broken for multi-IRQ FlexCAN platforms (like S32N79) because `enable_irq_wake()` is called on the mailbox interrupt (`dev->irq`) instead of the state/wakeup interrupt (`priv->irq_err`).
--
commit 39bd2be7b5ab93fd5fb7064b8e7d3eac344ed38f
Author: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
can: flexcan: add NXP S32N79 SoC support
This patch introduces support for the NXP S32N79 SoC in the FlexCAN driver.
It adds a new device data structure specifying necessary quirks, including
multiple interrupt handling, and registers the new compatible string.
> diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c
> --- a/drivers/net/can/flexcan/flexcan-core.c
> +++ b/drivers/net/can/flexcan/flexcan-core.c
> @@ -397,6 +397,15 @@ static const struct flexcan_devtype_data nxp_s32g2_devtype_data = {
> FLEXCAN_QUIRK_SECONDARY_MB_IRQ,
> };
>
> +static const struct flexcan_devtype_data nxp_s32n_devtype_data = {
> + .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
> + FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
> + FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_FD |
> + FLEXCAN_QUIRK_SUPPORT_ECC | FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
> + FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR |
> + FLEXCAN_QUIRK_IRQ_BERR,
[Severity: High]
This isn't a bug introduced by this patch, but will wakeup functionality be
broken for this new platform since it uses multiple interrupts?
In flexcan_suspend() and flexcan_resume(), the driver hardcodes
enable_irq_wake(dev->irq) and disable_irq_wake(dev->irq):
flexcan_suspend() {
...
if (device_may_wakeup(device)) {
enable_irq_wake(dev->irq);
...
}
For multi-IRQ platforms using FLEXCAN_QUIRK_IRQ_BERR, dev->irq is dedicated
to mailboxes, while state changes and wakeups (FLEXCAN_ESR_WAK_INT) are
routed to priv->irq_err.
Because enable_irq_wake() is never called for priv->irq_err, will the
interrupt controller mask the actual wakeup interrupt during suspend,
preventing the CAN controller from waking up the CPU?
> +};
> +
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260603071342.641874-1-ciprianmarian.costea@oss.nxp.com?part=6
next prev parent reply other threads:[~2026-06-03 8:25 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-03 7:13 [PATCH RESEND v4 0/8] can: flexcan: Add NXP S32N79 SoC support Ciprian Costea
2026-06-03 7:13 ` [PATCH RESEND v4 1/8] can: flexcan: use dedicated IRQ handlers for multi-IRQ platforms Ciprian Costea
2026-06-03 7:29 ` sashiko-bot
2026-06-03 10:06 ` Enric Balletbo i Serra
2026-06-03 7:13 ` [PATCH RESEND v4 2/8] can: flexcan: disable all IRQ lines in flexcan_chip_interrupts_enable() Ciprian Costea
2026-06-03 7:13 ` [PATCH RESEND v4 3/8] can: flexcan: split rx/tx masks per mailbox IRQ line Ciprian Costea
2026-06-03 7:49 ` sashiko-bot
2026-06-03 7:13 ` [PATCH RESEND v4 4/8] dt-bindings: can: fsl,flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-06-03 8:02 ` sashiko-bot
2026-06-03 7:13 ` [PATCH RESEND v4 5/8] can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk Ciprian Costea
2026-06-03 8:15 ` sashiko-bot
2026-06-03 7:13 ` [PATCH RESEND v4 6/8] can: flexcan: add NXP S32N79 SoC support Ciprian Costea
2026-06-03 8:25 ` sashiko-bot [this message]
2026-06-03 7:13 ` [PATCH RESEND v4 7/8] arm64: dts: s32n79: add FlexCAN nodes Ciprian Costea
2026-06-03 7:13 ` [PATCH RESEND v4 8/8] arm64: dts: s32n79: enable FlexCAN devices Ciprian Costea
2026-06-03 9:39 ` [PATCH RESEND v4 0/8] can: flexcan: Add NXP S32N79 SoC support Bough Chen
2026-06-03 10:28 ` Enric Balletbo i Serra
2026-06-03 10:33 ` Ciprian Marian Costea
-- strict thread matches above, loose matches on Subject: below --
2026-04-21 10:25 Ciprian Costea
2026-04-21 10:26 ` [PATCH RESEND v4 6/8] can: flexcan: add " Ciprian Costea
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