Re: [PATCH 4/5] soc: qcom: ubwc: Add Shikra UBWC config

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Assigning `no_ubwc_data` to the modern DPU-based Shikra platform causes an integer underflow in the MDSS display driver. `no_ubwc_data` zero-initializes `.highest_bank_bit`. For older MDP5 platforms, this is safe because `msm_mdss_enable()` skips UBWC setup entirely. However, Shikra is a modern DPU platform (MDSS HW ver 6.5), so `msm_mdss_enable()` unconditionally calls `msm_mdss_6x_setup_ubwc()`. This function executes `MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13)`. With `highest_bank_bit == 0`, this underflows to `-13`, writing garbage configuration bits to the `REG_MDSS_UBWC_STATIC` hardware register. Additionally, this introduces a latent kernel panic: if an Adreno GPU driver is later enabled for Shikra, `a6xx_set_ubwc_config()` will trigger an unconditional `BUG_ON(cfg->highest_bank_bit < 13)` during probe. The correct approach for modern platforms without UBWC is to supply a dummy configuration with `.highest_bank_bit >= 13` (as seen in `qcm2290_data` which sets it to 15).
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commit 75083d2d954151a192078564961f45c04709ad91
Author: Nabige Aala <nabige.aala@oss.qualcomm.com>

soc: qcom: ubwc: Add Shikra UBWC config

Add UBWC configuration for the Shikra platform. Shikra has no UBWC
support and no highest_bank_bit setting, so use no_ubwc_data.

> diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
> index 3fe47d8f0f638..01dca97e26714 100644
> --- a/drivers/soc/qcom/ubwc_config.c
> +++ b/drivers/soc/qcom/ubwc_config.c
> @@ -278,6 +278,7 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
>  	{ .compatible = "qcom,sdm660", .data = &msm8937_data },
>  	{ .compatible = "qcom,sdm670", .data = &sdm670_data, },
>  	{ .compatible = "qcom,sdm845", .data = &sdm845_data, },
> +	{ .compatible = "qcom,shikra", .data = &no_ubwc_data, },

[Severity: High]
Will using no_ubwc_data cause an integer underflow on modern DPU platforms?

The no_ubwc_data structure zero-initializes the highest_bank_bit field.
Because Shikra is a modern DPU platform, msm_mdss_enable() unconditionally
calls msm_mdss_6x_setup_ubwc() in drivers/gpu/drm/msm/msm_mdss.c, which
performs this calculation:

    MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);

If highest_bank_bit is 0, this results in -13 and writes corrupted bits
to the REG_MDSS_UBWC_STATIC hardware register.

Additionally, will this configuration trigger a kernel panic if an Adreno
GPU driver is later enabled? In a6xx_set_ubwc_config(), there is an
unconditional check:

    BUG_ON(cfg->highest_bank_bit < 13);

Should this platform instead use a dummy configuration with highest_bank_bit
set to a value >= 13, similar to how qcm2290_data sets it to 15?

>  	{ .compatible = "qcom,sm4250", .data = &sm6115_data, },
>  	{ .compatible = "qcom,sm6115", .data = &sm6115_data, },
>  	{ .compatible = "qcom,sm6125", .data = &sm6125_data, },

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260603-shikra-display-v1-0-aeac1b94faa7@oss.qualcomm.com?part=4