Re: [PATCH 4/7] dt-bindings: timer: Add RISC-V ACLINT bindings

[Conor Dooley <conor@kernel.org>]

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On Fri, Jun 05, 2026 at 12:09:06AM +0930, Joel Stanley wrote:
> On Wed, 3 Jun 2026 at 18:53, Conor Dooley <conor@kernel.org> wrote:
> >
> > On Wed, Jun 03, 2026 at 05:12:16PM +0930, Joel Stanley wrote:
> > > Document the bindings for the RISC-V ACLINT.
> > >
> > > Signed-off-by: Drew Fustini <fustini@kernel.org>
> > > Signed-off-by: Joel Stanley <joel@jms.id.au>
> > > ---
> > >  MAINTAINERS                                   |  1 +
> > >  .../bindings/timer/riscv,aclint-mtimer.yaml   | 52 +++++++++++++++++++
> > >  2 files changed, 53 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> > >
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 2fb1c75afd16..43dd9873bbc5 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -23005,6 +23005,7 @@ M:    Joel Stanley <jms@oss.tenstorrent.com>
> > >  L:   linux-riscv@lists.infradead.org
> > >  S:   Maintained
> > >  T:   git https://github.com/tenstorrent/linux.git
> > > +F:   Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> > >  F:   Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
> > >  F:   Documentation/devicetree/bindings/riscv/tenstorrent.yaml
> > >  F:   arch/riscv/boot/dts/tenstorrent/
> > > diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> > > new file mode 100644
> > > index 000000000000..192ff3fcf79f
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> > > @@ -0,0 +1,52 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: RISC-V Advanced Core Local Interruptor (ACLINT)
> > > +
> > > +maintainers:
> > > +  - Joel Stanley <jms@oss.tenstorrent.com>
> > > +
> > > +description:
> > > +  This RISC-V ACLINT specification defines a set of memory mapped devices which
> > > +  provide inter-processor interrupts (IPI) and timer functionalities for each
> > > +  HART on a multi-HART RISC-V platform. The specification can be found at
> > > +  https://github.com/riscvarchive/riscv-aclint/
> >
> > This is a draft specification, so having a "riscv,aclint-mtimer"
> > compatible is not appropriate. Ordinarily I would say that you should be
> > able to do this once frozen, but this spec is archived and unlikely to
> > have that happen.
> 
> I've reworked the binding to reference the privileged spec, which is
> ratified and has a section on the timer registers:
> 
>  https://docs.riscv.org/reference/isa/priv/machine.html#3-1-2-1-machine-timer-mtime-and-mtimecmp-registers
> 
> I'll post a v2 now for review.

To be clear, the problem isn't referencing the draft spec (that is what
you implemented after all). It's the "riscv,aclint-mtimer" compatible
that's the problem.

Cheers,
Conor.

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