* [PATCH v6 00/11] Add Renesas RZ/G3E GPT support
@ 2026-06-04 9:56 Biju
2026-06-04 9:56 ` [PATCH v6 02/11] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Biju
2026-06-04 9:56 ` [PATCH v6 10/11] dt-bindings: pwm: Document RZ/G3E GPT support Biju
0 siblings, 2 replies; 4+ messages in thread
From: Biju @ 2026-06-04 9:56 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Philipp Zabel
Cc: Biju Das, linux-pwm, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
This series extends the RZ/G2L GPT PWM driver with RZ/G3E SoC support.
The RZ/G3E GPT has a number of hardware differences compared to RZ/G2L:
it exposes 16 channels (across two GPT instances of 8 channels each),
uses a 4-bit GTCR prescaler field (versus 3-bit on RZ/G2L), and has a
discontinuous prescale sequence with powers-of-2 scaling rather than the
continuous powers-of-4 sequence on RZ/G2L. It also has additional clocks
and resets (bus clock and rst_s).
To accommodate these differences cleanly the series proceeds as follows:
Patch 1 fixes overflow with period_ticks variable.
Patches 2-3 add DT binding documentation for the renesas,poegs property
(allowing GPT channels to be linked with POEG for output-disable) and
implement the corresponding driver support. This configures GTINTAD to
route output-disable requests to the correct POEG group and sets GTIOR
to tri-state both output pins on an output-disable event.
Patch 4-5 small cleanup adding missing newlines to dev_err_probe()
messages and removing an unused parameter from
rzg2l_gpt_calculate_prescale().
Patch 6 migrates the driver from the legacy .get_state/.apply ops to
the new waveform callback interface, introducing struct
rzg2l_gpt_waveform to hold the hardware configuration (gtpr, gtccr,
prescale) for a single channel.
Patches 7-9 introduce struct rzg2l_gpt_info to capture SoC-specific
hardware differences, adding fields for the GTCR prescaler mask
(gtcr_tpcs), the prescaler multiplier (prescale_mult), and a
calculate_prescale() function pointer. This cleanly abstracts the
per-SoC prescaler logic needed for RZ/G3E.
Patch 10 adds DT binding documentation for the RZ/G3E GPT
(renesas,r9a09g047-gpt), covering its 16-channel layout, 64 interrupts,
dual clocks and dual resets.
Patch 11 adds the RZ/G3E driver support itself, wiring up the new
rzg3e_data match entry with its own prescale calculation, prescaler
field mask, and prescale multiplier.
v5->v6:
* Added patch for fixing period_ticks overflow.
* Added patch to add missing newlines to dev_err_probe() messages.
* Dropped extra space in poegs variable assignment in
rzg2l_gpt_poeg_init().
* Updated the comment sections of rzg2l_gpt_poeg_init() with POEG and GPT
in upper-case and replaced configure->configures.
* Format specifiers in dev_err() changed from %d to %u in
rzg2l_gpt_poeg_init().
* Dropped local variables pv and dc from rzg2l_gpt_round_waveform_tohw().
* Dropped blank line in rzg2l_gpt_round_waveform_tohw().
* Moved assignment of rzg2l_gpt->period_ticks[ch] to *_write_waveform().
* Restored clamping of duty_ticks with period_ticks in
rzg2l_gpt_round_waveform_tohw().
* Simplified rzg2l_gpt_write_waveform() using else if statement.
* Dropped local variable gptr in rzg2l_gpt_write_waveform().
* Moved mutex after early return in rzg2l_gpt_round_waveform_tohw().
* Dropped extra parameter rzg2l_gpt from rzg2l_gpt_calculate_prescale()
in rzg2l_gpt_round_waveform_tohw().
* Updated comment in rzg2l_gpt_calculate_period_or_duty().
* Updated rzg3e_gpt_calculate_prescale().
v4->v5:
* Merged GPT linking POEG patch series here.
* Dropped suspend/resume patch; will be added later.
* Updated commit description for patches #2, #4, #5, and #6.
* Replaced return type of rzg2l_gpt_poeg_init() from void to int and
probe() check this return value.
* Added more error checks in rzg2l_gpt_poeg_init().
* Added a patch to drop the unused rzg2l_gpt_chip parameter from
rzg2l_gpt_calculate_prescale().
* Updated rzg2l_gpt_round_waveform_tohw() to initialize gtccr when the
period of the second channel is smaller.
* Replaced period_ticks with RZG2L_MAX_TICKS for the duty_ticks maximum
value check in rzg2l_gpt_round_waveform_tohw().
v3->v4:
* Added wave form callback conversion back to this patch series.
* Updated rzg2l_gpt_is_ch_enabled() fit into 80-character limit for
consistency with other functions.
* Dropped field_{get,prep} as mainline now support it.
* Updated commit description for patch#3
* Retained RZG2L_GTCR_TPCS bit definitons
* Replaced gtcr_tpcs_mask->gtcr_tpcs
* Updated commit header and description for patch#4
* Renamed prescale_pow_of_two_mult_factor->prescale_mult
* Added RZG3E_GTCR_TPCS bit definition for RZ/G3E and added to
rzg3e_data.
* Added error checks on suspend() and device set to operational state
on failure().
* Added Rb tag from Geert for SoC dtsi.
* Added SW_GPIO9_CAN1_STB check to gpt0 node.
v2->v3:
* Added Rb tag from Rob for bindings patch
* Dropped wave form callback conversion from this patch series as
it is covered in another series[1]
* Added suspend/resume support.
v1->v2:
* Created separate document for RZ/G3E GPT.
* Updated commit header and description for binding patch.
* Added waveform callback conversion to this series.
* Collected tag.
* Added link to hardware manual
* Updated limitation section in driver patch.
Biju Das (11):
pwm: rzg2l-gpt: Fix period_ticks type from u32 to u64
dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property
pwm: rzg2l-gpt: Add support for gpt linking with poeg
pwm: rzg2l-gpt: Add missing newlines to dev_err_probe() messages
pwm: rzg2l-gpt: Drop unused rzg2l_gpt_chip parameter from
rzg2l_gpt_calculate_prescale()
pwm: rzg2l-gpt: Convert to waveform callbacks
pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip
pwm: rzg2l-gpt: Add prescale_mult variable to struct rzg2l_gpt_info
pwm: rzg2l-gpt: Add calculate_prescale() callback to struct
rzg2l_gpt_info
dt-bindings: pwm: Document RZ/G3E GPT support
pwm: rzg2l-gpt: Add RZ/G3E support
.../bindings/pwm/renesas,rzg2l-gpt.yaml | 23 ++
.../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 +++++++++++++++
drivers/pwm/pwm-rzg2l-gpt.c | 379 +++++++++++++-----
3 files changed, 634 insertions(+), 91 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml
base-commit: 5b5e33c44a491d5b5e019f527e028bd567a226fa
--
2.43.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v6 02/11] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property
2026-06-04 9:56 [PATCH v6 00/11] Add Renesas RZ/G3E GPT support Biju
@ 2026-06-04 9:56 ` Biju
2026-06-04 10:06 ` sashiko-bot
2026-06-04 9:56 ` [PATCH v6 10/11] dt-bindings: pwm: Document RZ/G3E GPT support Biju
1 sibling, 1 reply; 4+ messages in thread
From: Biju @ 2026-06-04 9:56 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G2L GPT IP supports output pin disable function by dead time
error and detecting short-circuits between output pins.
Add documentation for the optional property renesas,poegs to
link a pair of GPT IOs with POEG.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v5->v6:
* No change
v5:
* No change
v24 from [1]:
[1] https://lore.kernel.org/all/20250226144531.176819-1-biju.das.jz@bp.renesas.com/
---
.../bindings/pwm/renesas,rzg2l-gpt.yaml | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
index 13b807765a30..98bcde755fb9 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
@@ -245,6 +245,28 @@ properties:
resets:
maxItems: 1
+ renesas,poegs:
+ minItems: 1
+ maxItems: 8
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle to POEG instance that serves the output disable
+ - enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
+ description: |
+ An index identifying pair of GPT channels.
+ <0> : GPT channels 0 and 1
+ <1> : GPT channels 2 and 3
+ <2> : GPT channels 4 and 5
+ <3> : GPT channels 6 and 7
+ <4> : GPT channels 8 and 9
+ <5> : GPT channels 10 and 11
+ <6> : GPT channels 12 and 13
+ <7> : GPT channels 14 and 15
+ description:
+ A list of phandle and channel index pair tuples to the POEGs that handle the
+ output disable for the GPT channels.
+
required:
- compatible
- reg
@@ -375,4 +397,5 @@ examples:
power-domains = <&cpg>;
resets = <&cpg R9A07G044_GPT_RST_C>;
#pwm-cells = <3>;
+ renesas,poegs = <&poeggd 4>;
};
--
2.43.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v6 10/11] dt-bindings: pwm: Document RZ/G3E GPT support
2026-06-04 9:56 [PATCH v6 00/11] Add Renesas RZ/G3E GPT support Biju
2026-06-04 9:56 ` [PATCH v6 02/11] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Biju
@ 2026-06-04 9:56 ` Biju
1 sibling, 0 replies; 4+ messages in thread
From: Biju @ 2026-06-04 9:56 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Document support for the GPT found on the Renesas RZ/G3E (R9A09G047)
SoC.
The GPT is a 32-bit timer with 16 hardware channels (GPT0: 8 channel
and GPT1: 8channels). The hardware supports simultaneous control of
all channels. PWM waveforms can be generated by controlling the
up-counter, downcounter, or up- and down-counter.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* Added Rb tag from Rob.
v1->v2:
* Created separate document for RZ/G3E GPT.
* Updated commit header and description.
---
.../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 ++++++++++++++++++
1 file changed, 323 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml
new file mode 100644
index 000000000000..cb4ffab5f47f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml
@@ -0,0 +1,323 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/renesas,rzg3e-gpt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3E General PWM Timer (GPT)
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ RZ/G3E General PWM Timer (GPT) composed of 16 channels with 32-bit
+ timer. It supports the following functions
+ * 32 bits x 16 channels.
+ * Up-counting or down-counting (saw waves) or up/down-counting
+ (triangle waves) for each counter.
+ * Clock sources independently selectable for each channel.
+ * Four I/O pins per channel.
+ * Two output compare/input capture registers per channel.
+ * For the two output compare/input capture registers of each channel,
+ four registers are provided as buffer registers and are capable of
+ operating as comparison registers when buffering is not in use.
+ * In output compare operation, buffer switching can be at crests or
+ troughs, enabling the generation of laterally asymmetric PWM waveforms.
+ * Registers for setting up frame cycles in each channel (with capability
+ for generating interrupts at overflow or underflow)
+ * Generation of dead times in PWM operation.
+ * Synchronous starting, stopping and clearing counters for arbitrary
+ channels.
+ * Count start, count stop, count clear, up-count, down-count, or input
+ capture operation in response to a maximum of 8 ELC events.
+ * Count start, count stop, count clear, up-count, down-count, or input
+ capture operation in response to the status of two input pins.
+ * Starting, clearing, stopping and up/down counters in response to a
+ maximum of four external triggers.
+ * Output pin disable function by detected short-circuits between output
+ pins.
+ * A/D converter start triggers can be generated.
+ * Compare match A to F event and overflow/underflow event can be output
+ to the ELC.
+ * Enables the noise filter for input capture.
+ * Logical operation between the channel output.
+
+properties:
+ compatible:
+ items:
+ - const: renesas,r9a09g047-gpt # RZ/G3E
+
+ reg:
+ maxItems: 1
+
+ '#pwm-cells':
+ const: 3
+
+ interrupts:
+ items:
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.0
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.0
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.0
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.0
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.0
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.0
+ - description: A and B both high interrupt for channel GPT{0,1}.0
+ - description: A and B both low interrupt for channel GPT{0,1}.0
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.1
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.1
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.1
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.1
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.1
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.1
+ - description: A and B both high interrupt for channel GPT{0,1}.1
+ - description: A and B both low interrupt for channel GPT{0,1}.1
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.2
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.2
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.2
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.2
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.2
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.2
+ - description: A and B both high interrupt for channel GPT{0,1}.2
+ - description: A and B both low interrupt for channel GPT{0,1}.2
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.3
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.3
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.3
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.3
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.3
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.3
+ - description: A and B both high interrupt for channel GPT{0,1}.3
+ - description: A and B both low interrupt for channel GPT{0,1}.3
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.4
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.4
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.4
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.4
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.4
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.4
+ - description: A and B both high interrupt for channel GPT{0,1}.4
+ - description: A and B both low interrupt for channel GPT{0,1}.4
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.5
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.5
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.5
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.5
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.5
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.5
+ - description: A and B both high interrupt for channel GPT{0,1}.5
+ - description: A and B both low interrupt for channel GPT{0,1}.5
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.6
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.6
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.6
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.6
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.6
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.6
+ - description: A and B both high interrupt for channel GPT{0,1}.6
+ - description: A and B both low interrupt for channel GPT{0,1}.6
+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.7
+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.7
+ - description: Compare match with the GTCCRC for channel GPT{0,1}.7
+ - description: Compare match with the GTCCRD for channel GPT{0,1}.7
+ - description: Compare match with the GTCCRE for channel GPT{0,1}.7
+ - description: Compare match with the GTCCRF for channel GPT{0,1}.7
+ - description: A and B both high interrupt for channel GPT{0,1}.7
+ - description: A and B both low interrupt for channel GPT{0,1}.7
+
+ interrupt-names:
+ items:
+ - const: gtcia0
+ - const: gtcib0
+ - const: gtcic0
+ - const: gtcid0
+ - const: gtcie0
+ - const: gtcif0
+ - const: gtcih0
+ - const: gtcil0
+ - const: gtcia1
+ - const: gtcib1
+ - const: gtcic1
+ - const: gtcid1
+ - const: gtcie1
+ - const: gtcif1
+ - const: gtcih1
+ - const: gtcil1
+ - const: gtcia2
+ - const: gtcib2
+ - const: gtcic2
+ - const: gtcid2
+ - const: gtcie2
+ - const: gtcif2
+ - const: gtcih2
+ - const: gtcil2
+ - const: gtcia3
+ - const: gtcib3
+ - const: gtcic3
+ - const: gtcid3
+ - const: gtcie3
+ - const: gtcif3
+ - const: gtcih3
+ - const: gtcil3
+ - const: gtcia4
+ - const: gtcib4
+ - const: gtcic4
+ - const: gtcid4
+ - const: gtcie4
+ - const: gtcif4
+ - const: gtcih4
+ - const: gtcil4
+ - const: gtcia5
+ - const: gtcib5
+ - const: gtcic5
+ - const: gtcid5
+ - const: gtcie5
+ - const: gtcif5
+ - const: gtcih5
+ - const: gtcil5
+ - const: gtcia6
+ - const: gtcib6
+ - const: gtcic6
+ - const: gtcid6
+ - const: gtcie6
+ - const: gtcif6
+ - const: gtcih6
+ - const: gtcil6
+ - const: gtcia7
+ - const: gtcib7
+ - const: gtcic7
+ - const: gtcid7
+ - const: gtcie7
+ - const: gtcif7
+ - const: gtcih7
+ - const: gtcil7
+
+ clocks:
+ items:
+ - description: Core clock (PCLKD)
+ - description: Bus clock (PCLKA)
+
+ clock-names:
+ items:
+ - const: core
+ - const: bus
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ items:
+ - description: Reset for bus clock (PCLKA/PCLKD)
+ - description: Reset for core clock (PCLKD)
+
+ reset-names:
+ items:
+ - const: rst_p
+ - const: rst_s
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: pwm.yaml#
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pwm@13010000 {
+ compatible = "renesas,r9a09g047-gpt";
+ reg = <0x13010000 0x10000>;
+ interrupts = <GIC_SPI 538 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 554 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 562 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 570 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 586 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 594 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 539 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 555 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 563 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 571 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 579 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 540 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 548 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 556 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 572 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 580 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 588 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 541 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 549 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 557 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 573 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 581 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 589 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 597 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 542 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 550 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 558 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 566 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 582 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 590 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 598 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 543 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 551 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 559 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 567 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 575 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 583 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 544 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 552 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 560 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 568 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 584 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 553 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 561 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 569 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 577 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 593 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "gtcia0", "gtcib0", "gtcic0", "gtcid0",
+ "gtcie0", "gtcif0", "gtcih0", "gtcil0",
+ "gtcia1", "gtcib1", "gtcic1", "gtcid1",
+ "gtcie1", "gtcif1", "gtcih1", "gtcil1",
+ "gtcia2", "gtcib2", "gtcic2", "gtcid2",
+ "gtcie2", "gtcif2", "gtcih2", "gtcil2",
+ "gtcia3", "gtcib3", "gtcic3", "gtcid3",
+ "gtcie3", "gtcif3", "gtcih3", "gtcil3",
+ "gtcia4", "gtcib4", "gtcic4", "gtcid4",
+ "gtcie4", "gtcif4", "gtcih4", "gtcil4",
+ "gtcia5", "gtcib5", "gtcic5", "gtcid5",
+ "gtcie5", "gtcif5", "gtcih5", "gtcil5",
+ "gtcia6", "gtcib6", "gtcic6", "gtcid6",
+ "gtcie6", "gtcif6", "gtcih6", "gtcil6",
+ "gtcia7", "gtcib7", "gtcic7", "gtcid7",
+ "gtcie7", "gtcif7", "gtcih7", "gtcil7";
+ clocks = <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>;
+ clock-names = "core", "bus";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x59>, <&cpg 0x5a>;
+ reset-names = "rst_p", "rst_s";
+ #pwm-cells = <3>;
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v6 02/11] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property
2026-06-04 9:56 ` [PATCH v6 02/11] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Biju
@ 2026-06-04 10:06 ` sashiko-bot
0 siblings, 0 replies; 4+ messages in thread
From: sashiko-bot @ 2026-06-04 10:06 UTC (permalink / raw)
To: Biju; +Cc: wsa+renesas, robh, conor+dt, devicetree
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `renesas,poegs` property improperly encodes the consumer's channel index as a phandle specifier, which is a Devicetree anti-pattern and breaks standard phandle-array parsing semantics.
--
commit 9d7f9847d3f320fb715022b6159c9c7e869aeedd
Author: Biju Das <biju.das.jz@bp.renesas.com>
dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property
RZ/G2L GPT IP supports output pin disable function by dead time
error and detecting short-circuits between output pins.
Add documentation for the optional property renesas,poegs to
link a pair of GPT IOs with POEG.
> diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
[ ... ]
> @@ -245,6 +245,28 @@ properties:
> resets:
> maxItems: 1
>
> + renesas,poegs:
> + minItems: 1
> + maxItems: 8
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: phandle to POEG instance that serves the output disable
> + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
> + description: |
> + An index identifying pair of GPT channels.
[Severity: Medium]
Does this property correctly follow standard Devicetree phandle semantics?
By Devicetree specification, phandle arguments in a phandle-array are
defined and interpreted by the target provider node, with their length
dictated by a cell-count property on the provider.
This definition appears to invert that model by using the specifier to encode
the consumer's (GPT) own channel index rather than a provider argument.
Additionally, standard OS-agnostic DT parsers might fail to resolve this
because the referenced provider binding (renesas,rzg2l-poeg.yaml) enforces
additionalProperties: false and natively lacks a #poeg-cells property to
dictate the specifier length.
Is it possible to redesign this binding so it doesn't encode the consumer's
index into the provider's phandle argument, or at least ensure the POEG
provider specifies a #poeg-cells property?
> + <0> : GPT channels 0 and 1
> + <1> : GPT channels 2 and 3
> + <2> : GPT channels 4 and 5
> + <3> : GPT channels 6 and 7
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260604095647.108654-1-biju.das.jz@bp.renesas.com?part=2
^ permalink raw reply [flat|nested] 4+ messages in thread
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Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-06-04 9:56 [PATCH v6 00/11] Add Renesas RZ/G3E GPT support Biju
2026-06-04 9:56 ` [PATCH v6 02/11] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Biju
2026-06-04 10:06 ` sashiko-bot
2026-06-04 9:56 ` [PATCH v6 10/11] dt-bindings: pwm: Document RZ/G3E GPT support Biju
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