[PATCH v11 0/3] Add eDP support for RK3576

[PATCH v11 0/3] Add eDP support for RK3576

[Damon Ding]

Picked from:
https://lore.kernel.org/all/20260601065100.1103873-1-damon.ding@rock-chips.com/

Patch 1-2 are to add missing clock "hclk" for RK3588 eDP nodes.
Patch 3 is to add the RK3576 eDP node.

Damon Ding (3):
  arm64: dts: rockchip: Add missing hclk for RK3588 eDP0
  arm64: dts: rockchip: Add missing hclk for RK3588 eDP1
  arm64: dts: rockchip: Add eDP node for RK3576

 arch/arm64/boot/dts/rockchip/rk3576.dtsi      | 28 +++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi |  4 +--
 .../arm64/boot/dts/rockchip/rk3588-extra.dtsi |  4 +--
 3 files changed, 32 insertions(+), 4 deletions(-)

---

Changes in v2:
- Split out separate patches to add the "hclk" clock reference.
- Split out separate patches to enable the "hclk" clock.
- Add Reviewed-by tag.

Changes in v3:
- Add a patch to expand descriptions for clocks of the eDP node.
- Add Reviewed-by tag.

Changes in v4:
- Modify commit msg.

Changes in v5:
- Enforce the correct third clock name on a per-compatible basis.
- Modify the commit msg simultaneously.
- Add Acked-by tag.

Changes in v6:
- Expand more detail commit msg about using hclk instead of grf clock.

Changes in v7:
- List all valid clock names at the top level, and constrain the clock
  count for each platform with minItems/maxItems in allOf.

Changes in v8:
- Fix indentation to 10 for enum in clock-names property.

Changes in v9:
- Restore the explicit clock-names for RK3399 and RK3588 eDP dt-bindings.

Changes in v10:
- Use automatic cleanup to fix OF node reference leak reported by
  Sashiko.

Changes in v11:
- Pick and rebase DT related patches.

-- 
2.34.1

[PATCH v11 1/3] arm64: dts: rockchip: Add missing hclk for RK3588 eDP0

[Damon Ding]

Add the required HCLK_VO1 bus clock to RK3588 eDP0 node with
corresponding clock-name "hclk". This clock is necessary for the
eDP controller to access video output GRF and work properly.

Previously the clock was enabled implicitly via GRF phandle
reference. Add it explicitly now to align with updated binding.

Fixes: dc79d3d5e7c7 ("arm64: dts: rockchip: Add eDP0 node for RK3588")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

---

Changes in v4:
- Modify the commit msg.
---
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 4fb8888c281c..24a5ccbac08c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1712,8 +1712,8 @@ hdmi0_out: port@1 {
 	edp0: edp@fdec0000 {
 		compatible = "rockchip,rk3588-edp";
 		reg = <0x0 0xfdec0000 0x0 0x1000>;
-		clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>;
-		clock-names = "dp", "pclk";
+		clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, <&cru HCLK_VO1>;
+		clock-names = "dp", "pclk", "hclk";
 		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
 		phys = <&hdptxphy0>;
 		phy-names = "dp";
-- 
2.34.1

[PATCH v11 2/3] arm64: dts: rockchip: Add missing hclk for RK3588 eDP1

[Damon Ding]

Add the required HCLK_VO1 bus clock to RK3588 eDP1 node with
corresponding clock-name "hclk". This clock is necessary for
the eDP controller to access video output GRF and work properly.

Previously the clock was enabled implicitly via GRF phandle
reference. Add it explicitly now to align with updated binding.

Fixes: a481bb0b1ad9 ("arm64: dts: rockchip: Add eDP1 dt node for rk3588")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

---

Changes in v4:
- Modify the commit msg.
---
 arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
index a2640014ee04..b251bb129cdb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -285,8 +285,8 @@ hdmi1_out: port@1 {
 	edp1: edp@fded0000 {
 		compatible = "rockchip,rk3588-edp";
 		reg = <0x0 0xfded0000 0x0 0x1000>;
-		clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>;
-		clock-names = "dp", "pclk";
+		clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>, <&cru HCLK_VO1>;
+		clock-names = "dp", "pclk", "hclk";
 		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
 		phys = <&hdptxphy1>;
 		phy-names = "dp";
-- 
2.34.1

[PATCH v11 3/3] arm64: dts: rockchip: Add eDP node for RK3576

[Damon Ding]

Add full device tree definition for the integrated eDP controller
on RK3576, following the existing RK3588 hardware layout.

Configure required register range, clocks, interrupt, phy, power
domain, reset and grf properties to fully describe the controller.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>

---

Changes in v2:
- Add Reviewed-by tag.

Changes in v4:
- Modify the commit msg.
---
 arch/arm64/boot/dts/rockchip/rk3576.dtsi | 28 ++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 28175d8200d5..733449cb88b1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1496,6 +1496,34 @@ hdmi_out: port@1 {
 			};
 		};
 
+		edp: edp@27dc0000 {
+			compatible = "rockchip,rk3576-edp";
+			reg = <0x0 0x27dc0000 0x0 0x1000>;
+			clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, <&cru HCLK_VO0_ROOT>;
+			clock-names = "dp", "pclk", "hclk";
+			interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&hdptxphy>;
+			phy-names = "dp";
+			power-domains = <&power RK3576_PD_VO0>;
+			resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
+			reset-names = "dp", "apb";
+			rockchip,grf = <&vo0_grf>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				edp_in: port@0 {
+					reg = <0>;
+				};
+
+				edp_out: port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
 		dp: dp@27e40000 {
 			compatible = "rockchip,rk3576-dp";
 			reg = <0x0 0x27e40000 0x0 0x30000>;
-- 
2.34.1

Re: [PATCH v11 2/3] arm64: dts: rockchip: Add missing hclk for RK3588 eDP1

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incorrect clock name "hclk" is used instead of "grf", which violates the DT binding schema and prevents the eDP driver from explicitly managing the clock.
--

commit a1adb5c9bb9ba76654d07ba8c6320c7edf51f41b
Author: Damon Ding <damon.ding@rock-chips.com>

arm64: dts: rockchip: Add missing hclk for RK3588 eDP1

This commit adds the required HCLK_VO1 bus clock to the RK3588 eDP1 node.
It intends to manage the clock explicitly instead of relying on implicit
enabling via the GRF phandle reference.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
> index a2640014ee042..b251bb129cdbf 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
> @@ -285,8 +285,8 @@ hdmi1_out: port@1 {
>  	edp1: edp@fded0000 {
>  		compatible = "rockchip,rk3588-edp";
>  		reg = <0x0 0xfded0000 0x0 0x1000>;
> -		clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>;
> -		clock-names = "dp", "pclk";
> +		clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>, <&cru HCLK_VO1>;
> +		clock-names = "dp", "pclk", "hclk";

[Severity: Medium]
Should this clock name be "grf" instead of "hclk"?

According to the device tree binding schema for rockchip,analogix-dp, the
third clock name is expected to be "grf".

The driver looks up this clock using devm_clk_get_optional(dev, "grf"). If
"hclk" is used here, the driver will fail to find it, receive a NULL
pointer, and won't explicitly enable the clock as intended by this patch.

>  		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
>  		phys = <&hdptxphy1>;
>  		phy-names = "dp";

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260605022305.3058853-1-damon.ding@rock-chips.com?part=2

Re: [PATCH v11 1/3] arm64: dts: rockchip: Add missing hclk for RK3588 eDP0

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch adds the `HCLK_VO1` clock to the `edp0` node but incorrectly names it `"hclk"` instead of `"grf"`. This violates the `rockchip,analogix-dp.yaml` DT schema, which strictly mandates the third clock to be named `"grf"`. Furthermore, it causes the driver's explicit clock management to silently fail: `analogix_dp-rockchip.c` requests the clock using `devm_clk_get_optional(dev, "grf")`. Because the DT name (`"hclk"`) does not match, the driver receives `NULL` and its explicit `clk_prepare_enable()` calls become no-ops.
--

commit 1f0c2ce9ff98f7230f0fe6e03686f09557a50f13
Author: Damon Ding <damon.ding@rock-chips.com>

arm64: dts: rockchip: Add missing hclk for RK3588 eDP0

This commit adds the HCLK_VO1 clock to the RK3588 eDP0 node. This is
intended to allow the eDP controller to correctly access the video output
GRF, transitioning from implicit enablement to explicit definition.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index 4fb8888c281c8..24a5ccbac08cb 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -1712,8 +1712,8 @@ hdmi0_out: port@1 {
>  	edp0: edp@fdec0000 {
>  		compatible = "rockchip,rk3588-edp";
>  		reg = <0x0 0xfdec0000 0x0 0x1000>;
> -		clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>;
> -		clock-names = "dp", "pclk";
> +		clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, <&cru HCLK_VO1>;
> +		clock-names = "dp", "pclk", "hclk";

[Severity: Medium]
Does naming this third clock "hclk" conflict with the driver's expectations
and the device tree schema?

The rockchip,analogix-dp.yaml schema expects the third clock to be named "grf".
Additionally, looking at rockchip_dp_of_probe() in the analogix_dp-rockchip.c
driver, it explicitly requests "grf":

drivers/gpu/drm/rockchip/analogix_dp-rockchip.c:rockchip_dp_of_probe() {
    ...
    dp->grfclk = devm_clk_get_optional(dev, "grf");
    ...
}

Because the name is specified as "hclk" here instead of "grf", will
devm_clk_get_optional() return a NULL pointer? This would cause the driver's
subsequent explicit clk_prepare_enable() calls for this clock to become
silent no-ops, bypassing the intended explicit clock management.

>  		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
>  		phys = <&hdptxphy0>;
>  		phy-names = "dp";

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260605022305.3058853-1-damon.ding@rock-chips.com?part=1

Re: [PATCH v11 3/3] arm64: dts: rockchip: Add eDP node for RK3576

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Missing dt-binding documentation and driver support for 'rockchip,rk3576-edp' compatible string.
- [Medium] Device tree schema violation and unmanaged clock due to incorrect clock-names mapping.
--

commit e47ec8c7e8e01e5a72a889c3a37a5a2d40321b07
Author: Damon Ding <damon.ding@rock-chips.com>

arm64: dts: rockchip: Add eDP node for RK3576
    
Add full device tree definition for the integrated eDP controller
on RK3576, following the existing RK3588 hardware layout.

> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> index 28175d8200d57..733449cb88b15 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
[ ... ]
> @@ -1496,6 +1496,34 @@ hdmi_out: port@1 {
>  			};
>  		};
>  
> +		edp: edp@27dc0000 {
> +			compatible = "rockchip,rk3576-edp";

[Severity: Medium]
Will this trigger a schema validation error during make dtbs_check?

The new compatible string is declared here without a fallback string like
"rockchip,rk3588-edp". If this string is not documented in the device tree
bindings (rockchip,analogix-dp.yaml) and lacks a match in the Rockchip Analogix
DP driver, the driver might not probe successfully. 

Should a fallback compatible be provided if the hardware is fully compatible,
or do the binding and driver need to be updated alongside this patch?

> +			reg = <0x0 0x27dc0000 0x0 0x1000>;
> +			clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, <&cru HCLK_VO0_ROOT>;
> +			clock-names = "dp", "pclk", "hclk";

[Severity: Medium]
Does naming this third clock "hclk" violate the device tree schema and
prevent the driver from managing it?

The dt-binding schema for rockchip,analogix-dp.yaml explicitly restricts the
third clock name to "grf". The eDP driver attempts to fetch the third clock
using devm_clk_get_optional(dev, "grf"). 

With the name set to "hclk" here, will the driver silently fail to find it,
causing the HCLK_VO0_ROOT clock to be ignored and left unprepared?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260605022305.3058853-1-damon.ding@rock-chips.com?part=3