Re: [PATCH v3 2/3] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incorrect `bus-range` property in PCI root port nodes causes primary and secondary bus numbers to overlap.
--

commit a2c7d2bee242af770a15bcba84f406c04640467d
Author: Ricardo Pardini <ricardo@pardini.net>

arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6

The FriendlyElec NanoPC-T6 carries two on-board Realtek RTL8125 NICs.
This commit describes the fixed function nodes and attaches ethernet aliases
so U-Boot can inject stable MAC addresses.

> --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi

[ ... ]

> @@ -635,6 +637,20 @@ &pcie2x1l0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pcie2_0_rst>;
>  	status = "okay";
> +
> +	pcie@0,0 {
> +		reg = <0x200000 0 0 0 0>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges;
> +		device_type = "pci";
> +		bus-range = <0x20 0x2f>;

[Severity: Medium]
Does this bus-range create an overlapping PCI topology?

The reg property places the PCI-to-PCI bridge on primary bus 0x20, but the
bus-range property specifies the downstream secondary and subordinate bus
numbers starting at 0x20. This claims that the secondary bus perfectly
overlaps the primary bus.

Since the child ethernet node uses bus 0x21 (reg = <0x210000 0 0 0 0>),
should the bus-range start at 0x21 instead, such as <0x21 0x2f>?

> +
> +		rtl_eth0: ethernet@0,0 {
> +			compatible = "pci10ec,8125";
> +			reg = <0x210000 0 0 0 0>;
> +		};
> +	};
>  };

[ ... ]

> @@ -651,6 +667,20 @@ &pcie2x1l2 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pcie2_2_rst>;
>  	status = "okay";
> +
> +	pcie@0,0 {
> +		reg = <0x400000 0 0 0 0>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges;
> +		device_type = "pci";
> +		bus-range = <0x40 0x4f>;

[Severity: Medium]
Is this bus-range similarly overlapping?

Like the node above, the bridge is on primary bus 0x40, but this sets the
secondary bus to also start at 0x40. Since the child node is at 0x41,
would it be more accurate to set this bus-range to <0x41 0x4f>?

> +
> +		rtl_eth1: ethernet@0,0 {
> +			compatible = "pci10ec,8125";
> +			reg = <0x410000 0 0 0 0>;
> +		};
> +	};
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260605-rk3588-dts-rtl-eth-describe-dt-alias-v3-0-8a8857b39daf@pardini.net?part=2