* [PATCH v7 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle
2026-06-08 4:16 [PATCH v7 0/3] Enable Inline crypto engine for kodiak and monaco Neeraj Soni
@ 2026-06-08 4:16 ` Neeraj Soni
2026-06-08 4:30 ` sashiko-bot
2026-06-08 6:10 ` Kuldeep Singh
2026-06-08 4:16 ` [PATCH v7 2/3] arm64: dts: qcom: kodiak: enable the inline crypto engine for SDHC Neeraj Soni
2026-06-08 4:16 ` [PATCH v7 3/3] arm64: dts: qcom: monaco: " Neeraj Soni
2 siblings, 2 replies; 6+ messages in thread
From: Neeraj Soni @ 2026-06-08 4:16 UTC (permalink / raw)
To: ulf.hansson, robh, krzk+dt, conor+dt, andersson, konradybcio
Cc: linux-mmc, devicetree, linux-kernel, neeraj.soni, Abel Vesa,
Abhinaba Rakshit, Kuldeep Singh, Krzysztof Kozlowski
Starting with sc7280(kodiak), the ICE will have its own device-tree node.
So add the qcom,ice property to reference it.
To avoid double-modeling, when qcom,ice is present, disallow an embedded
ICE register region in the SDHCI node. Older SoCs without ICE remain
valid as no additional requirement is imposed.
Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Co-developed-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260310113557.348502-2-neeraj.soni@oss.qualcomm.com
Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
---
.../bindings/mmc/qcom,sdhci-msm.yaml | 95 +++++++++++++------
1 file changed, 67 insertions(+), 28 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml
index bd558a11b792..b3fcc1673c10 100644
--- a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml
@@ -145,6 +145,11 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
description: platform specific settings for DLL_CONFIG reg.
+ qcom,ice:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the Inline Crypto Engine (ICE) hardware block for this controller.
+
iommus:
minItems: 1
maxItems: 8
@@ -198,35 +203,69 @@ allOf:
enum:
- qcom,sdhci-msm-v4
then:
- properties:
- reg:
- minItems: 2
- items:
- - description: Host controller register map
- - description: SD Core register map
- - description: CQE register map
- - description: Inline Crypto Engine register map
- reg-names:
- minItems: 2
- items:
- - const: hc
- - const: core
- - const: cqhci
- - const: ice
+ if:
+ required:
+ - qcom,ice
+ then:
+ properties:
+ reg:
+ minItems: 2
+ items:
+ - description: Host controller register map
+ - description: SD Core register map
+ - description: CQE register map
+ reg-names:
+ minItems: 2
+ items:
+ - const: hc
+ - const: core
+ - const: cqhci
+ else:
+ properties:
+ reg:
+ minItems: 2
+ items:
+ - description: Host controller register map
+ - description: SD Core register map
+ - description: CQE register map
+ - description: Inline Crypto Engine register map
+ reg-names:
+ minItems: 2
+ items:
+ - const: hc
+ - const: core
+ - const: cqhci
+ - const: ice
else:
- properties:
- reg:
- minItems: 1
- items:
- - description: Host controller register map
- - description: CQE register map
- - description: Inline Crypto Engine register map
- reg-names:
- minItems: 1
- items:
- - const: hc
- - const: cqhci
- - const: ice
+ if:
+ required:
+ - qcom,ice
+ then:
+ properties:
+ reg:
+ minItems: 1
+ items:
+ - description: Host controller register map
+ - description: CQE register map
+ reg-names:
+ minItems: 1
+ items:
+ - const: hc
+ - const: cqhci
+ else:
+ properties:
+ reg:
+ minItems: 1
+ items:
+ - description: Host controller register map
+ - description: CQE register map
+ - description: Inline Crypto Engine register map
+ reg-names:
+ minItems: 1
+ items:
+ - const: hc
+ - const: cqhci
+ - const: ice
unevaluatedProperties: false
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v7 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle
2026-06-08 4:16 ` [PATCH v7 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle Neeraj Soni
@ 2026-06-08 4:30 ` sashiko-bot
2026-06-08 6:10 ` Kuldeep Singh
1 sibling, 0 replies; 6+ messages in thread
From: sashiko-bot @ 2026-06-08 4:30 UTC (permalink / raw)
To: Neeraj Soni; +Cc: devicetree, conor+dt, robh
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incomplete DT binding constraint: The schema disallows the embedded `ice` register map when the `qcom,ice` phandle is present, but fails to disallow the embedded `ice` clock. This allows device trees to mistakenly specify both the `qcom,ice` phandle and the legacy `ice` clock on the SDHCI node, passing schema validation while double-modeling the clock resource.
--
commit 1a4e3c2586694f366860741fba23e497632a71fa
Author: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
dt-bindings: mmc: sdhci-msm: Add ICE phandle
This commit introduces the qcom,ice property to reference the Inline Crypto
Engine hardware block via a phandle. When this property is present, it
updates the allOf conditional blocks to disallow the embedded register
region in the SDHCI node to prevent double-modeling. Older SoCs without
this block remain unaffected.
Link: https://lore.kernel.org/r/20260310113557.348502-2-neeraj.soni@oss.qualcomm.com
> diff --git a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml
> index bd558a11b7929..b3fcc1673c106 100644
> --- a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml
> +++ b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml
[ ... ]
> @@ -198,35 +203,69 @@ allOf:
> enum:
> - qcom,sdhci-msm-v4
> then:
> - properties:
> - reg:
> - minItems: 2
> - items:
> - - description: Host controller register map
> - - description: SD Core register map
> - - description: CQE register map
> - - description: Inline Crypto Engine register map
> - reg-names:
> - minItems: 2
> - items:
> - - const: hc
> - - const: core
> - - const: cqhci
> - - const: ice
> + if:
> + required:
> + - qcom,ice
> + then:
> + properties:
> + reg:
> + minItems: 2
> + items:
> + - description: Host controller register map
> + - description: SD Core register map
> + - description: CQE register map
> + reg-names:
> + minItems: 2
> + items:
> + - const: hc
> + - const: core
> + - const: cqhci
[Severity: Medium]
Does this regression allow device trees to mistakenly specify the legacy "ice"
clock on the SDHCI node even when the "qcom,ice" phandle is present?
The commit message states the intent is to avoid double-modeling of the
Inline Crypto Engine block, and the allOf conditional block correctly
restricts the "ice" register map here. However, the schema doesn't seem to
disallow the embedded "ice" clock in clock-names when "qcom,ice" is provided.
Should there be corresponding restrictions for clock-names here to fully
prevent double-modeling the clock resource?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260608041650.541502-1-neeraj.soni@oss.qualcomm.com?part=1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v7 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle
2026-06-08 4:16 ` [PATCH v7 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle Neeraj Soni
2026-06-08 4:30 ` sashiko-bot
@ 2026-06-08 6:10 ` Kuldeep Singh
1 sibling, 0 replies; 6+ messages in thread
From: Kuldeep Singh @ 2026-06-08 6:10 UTC (permalink / raw)
To: Neeraj Soni, ulf.hansson, robh, krzk+dt, conor+dt, andersson,
konradybcio
Cc: linux-mmc, devicetree, linux-kernel, Abel Vesa, Abhinaba Rakshit,
Krzysztof Kozlowski
On 08-06-2026 09:46, Neeraj Soni wrote:
> Starting with sc7280(kodiak), the ICE will have its own device-tree node.
> So add the qcom,ice property to reference it.
>
> To avoid double-modeling, when qcom,ice is present, disallow an embedded
> ICE register region in the SDHCI node. Older SoCs without ICE remain
> valid as no additional requirement is imposed.
>
> Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> Co-developed-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> Link: https://lore.kernel.org/r/20260310113557.348502-2-neeraj.soni@oss.qualcomm.com
> Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
Link should go below "---" to specify previous discussions.
Usually maintainers add link of patchset being merged here while merging
changes in their tree but authors don't add it here.
--
Regards
Kuldeep
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v7 2/3] arm64: dts: qcom: kodiak: enable the inline crypto engine for SDHC
2026-06-08 4:16 [PATCH v7 0/3] Enable Inline crypto engine for kodiak and monaco Neeraj Soni
2026-06-08 4:16 ` [PATCH v7 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle Neeraj Soni
@ 2026-06-08 4:16 ` Neeraj Soni
2026-06-08 4:16 ` [PATCH v7 3/3] arm64: dts: qcom: monaco: " Neeraj Soni
2 siblings, 0 replies; 6+ messages in thread
From: Neeraj Soni @ 2026-06-08 4:16 UTC (permalink / raw)
To: ulf.hansson, robh, krzk+dt, conor+dt, andersson, konradybcio
Cc: linux-mmc, devicetree, linux-kernel, neeraj.soni, Kuldeep Singh
Add an ICE node to kodiak SoC description and enable it by adding a
phandle to the SDHC node.
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260310113557.348502-3-neeraj.soni@oss.qualcomm.com
Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index fa540d8c2615..caf4ec9cf9fc 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -1050,6 +1050,8 @@ sdhc_1: mmc@7c4000 {
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
+ qcom,ice = <&sdhc_ice>;
+
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
@@ -1076,6 +1078,13 @@ opp-384000000 {
};
};
+ sdhc_ice: crypto@7c8000 {
+ compatible = "qcom,sc7280-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x007c8000 0x0 0x18000>;
+ clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ };
+
gpi_dma0: dma-controller@900000 {
#dma-cells = <3>;
compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v7 3/3] arm64: dts: qcom: monaco: enable the inline crypto engine for SDHC
2026-06-08 4:16 [PATCH v7 0/3] Enable Inline crypto engine for kodiak and monaco Neeraj Soni
2026-06-08 4:16 ` [PATCH v7 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle Neeraj Soni
2026-06-08 4:16 ` [PATCH v7 2/3] arm64: dts: qcom: kodiak: enable the inline crypto engine for SDHC Neeraj Soni
@ 2026-06-08 4:16 ` Neeraj Soni
2 siblings, 0 replies; 6+ messages in thread
From: Neeraj Soni @ 2026-06-08 4:16 UTC (permalink / raw)
To: ulf.hansson, robh, krzk+dt, conor+dt, andersson, konradybcio
Cc: linux-mmc, devicetree, linux-kernel, neeraj.soni, Kuldeep Singh
Add an ICE node to monaco SoC description and enable it by adding a
phandle to the SDHC node.
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260310113557.348502-4-neeraj.soni@oss.qualcomm.com
Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/monaco.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index e4c8466f941b..06ed34dfe135 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -4835,6 +4835,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
supports-cqe;
dma-coherent;
+ qcom,ice = <&sdhc_ice>;
+
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
@@ -4867,6 +4869,13 @@ opp-384000000 {
};
};
+ sdhc_ice: crypto@87c8000 {
+ compatible = "qcom,qcs8300-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x087c8000 0x0 0x18000>;
+ clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ };
+
usb_1_hsphy: phy@8904000 {
compatible = "qcom,qcs8300-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread