Re: [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX8M-PLUS

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Orphaned pin configuration in `pinctrl_eqos` causes a pinctrl conflict, and missing PHY interrupt configuration.
--

commit 073a9021771cdebbb374385137ac2962db9362f2
Author: Stefano Radaelli <stefano.r@variscite.com>

arm64: dts: freescale: Add support for Variscite DART-MX8M-PLUS

Add device tree support for the Variscite DART-MX8MP system on module.
This SOM is designed to be used with various carrier boards.

Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-plus/dart-mx8m-plus/

> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtsi
> new file mode 100644
> index 0000000000000..a4563833ee8e0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtsi

[ ... ]

> +	mdio {
> +		compatible = "snps,dwmac-mdio";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethphy0: ethernet-phy@4 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <4>;
> +			reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
> +			reset-assert-us = <10000>;
> +			reset-deassert-us = <100000>;
> +			vddio-supply = <&reg_phy_vddio>;
> +		};

[Severity: Medium]
Does this PHY configuration omit the interrupt configuration?

Without the interrupt-parent and interrupts properties, will the kernel fall
back to CPU-intensive polling instead of interrupt-driven operation?

> +	};
> +};

[ ... ]

> +	pinctrl_eqos: eqosgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
> +			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2

[ ... ]

> +			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
> +			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
> +			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20					0x10

[Severity: Medium]
Is this pin erroneously claimed by the ethernet node?

This pin does not appear to be consumed by the Ethernet MAC or PHY in this
file. If a custom carrier board attempts to use SD2_WP for its standard
purpose or as a GPIO, will it fail with an -EBUSY pinctrl conflict because it
is locked here?

If this pin was originally intended to act as the PHY interrupt line, should
it be configured in the ethphy0 node instead?

> +			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11				0x150
> +		>;
> +	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1780912513.git.stefano.r@variscite.com?part=2