Re: [PATCH v2 3/3] arm64: dts: imx8mp-var-dart: Add support for Variscite Sonata board

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] RGMII TX pins are configured with minimum drive strength and slow slew rate.
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commit bdd50106871edf46aec2e0d2dd1a6553b8d8c5ed
Author: Stefano Radaelli <stefano.r@variscite.com>
arm64: dts: imx8mp-var-dart: Add support for Variscite Sonata board

This commit adds device tree support for the Variscite Sonata carrier board
equipped with the DART-MX8M-PLUS system on module. It defines nodes and
pinmux configurations for interfaces including Ethernet, USB, HDMI, and I2C
peripherals.

Link: https://variscite.com/carrier-boards/sonata-board/

> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-dart-sonata.dts
> new file mode 100644
> index 0000000000000..8afd72820f390
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-dart-sonata.dts

[ ... ]

> +	pinctrl_fec: fecgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90
> +			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90
> +			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90
> +			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x1d0
> +			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90
> +			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90
> +			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x00
> +			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x00
> +			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x00
> +			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x00
> +			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x00
> +			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x00

[Severity: High]
Will setting the pad values for the RGMII transmit pins to 0x00 cause signal
integrity problems?

A pad value of 0x00 sets the Drive Strength Enable (DSE) to its lowest setting
(X1) and the Fast Slew Rate (FSEL) to slow. RGMII operates at 125 MHz for
Gigabit Ethernet, which physically requires fast slew rates and higher drive
strength (typically 0x16 or 0x1f on i.MX devices) to maintain signal integrity.

Could these slow signal edges lead to CRC errors, link instability, or a
complete failure to establish a gigabit link under load?

> +		>;
> +	};

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Sashiko AI review · https://sashiko.dev/#/patchset/cover.1780912513.git.stefano.r@variscite.com?part=3