From: Conor Dooley <conor@kernel.org>
To: yunhui cui <cuiyunhui@bytedance.com>
Cc: akpm@linux-foundation.org, alex@ghiti.fr,
andrew+kernel@donnellan.id.au, aou@eecs.berkeley.edu,
apatel@ventanamicro.com, apopple@nvidia.com, atishp@rivosinc.com,
baolin.wang@linux.alibaba.com, cleger@rivosinc.com,
conor+dt@kernel.org, debug@rivosinc.com,
devicetree@vger.kernel.org, guodong@riscstar.com,
hui.wang@canonical.com, krzk+dt@kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
liu.xuemei1@zte.com.cn, namcao@linutronix.de, nick.hu@sifive.com,
palmer@dabbelt.com, pincheng.plct@isrc.iscas.ac.cn,
pjw@kernel.org, qingwei.hu@bytedance.com, ritesh.list@gmail.com,
rmclure@linux.ibm.com, robh@kernel.org, wangruikang@iscas.ac.cn,
zhangchunyan@iscas.ac.cn, zong.li@sifive.com
Subject: Re: [External] Re: [PATCH v3 1/3] dt-bindings: riscv: clarify Svadu boot-time behavior
Date: Wed, 10 Jun 2026 17:52:37 +0100 [thread overview]
Message-ID: <20260610-prompter-fever-db3f6a200051@spud> (raw)
In-Reply-To: <CAEEQ3w=C_z8awtevLhceTgqLW79ONzKTm5MRJeoSTLB9q_CeiQ@mail.gmail.com>
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On Wed, Jun 10, 2026 at 10:03:01AM +0800, yunhui cui wrote:
> Hi Conor,
>
> On Wed, Jun 10, 2026 at 12:09 AM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Tue, Jun 09, 2026 at 09:00:18PM +0800, Yunhui Cui wrote:
> > > Clarify that systems which advertise only Svadu have hardware PTE A/D
> > > updating enabled at boot, while systems advertising both Svade and Svadu
> > > must enable Svadu explicitly with SBI FWFT.
> > >
> > > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> > > Reviewed-by: Qingwei Hu <qingwei.hu@bytedance.com>
> > > ---
> > > Documentation/devicetree/bindings/riscv/extensions.yaml | 6 +++---
> > > 1 file changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > index 2b0a8a93bb214..b09888e9988de 100644
> > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > @@ -294,10 +294,10 @@ properties:
> > > of the PTE A/D bits or page faults when they need updated.
> > > 2) Only Svade present in DT => Supervisor must assume Svade to be
> > > always enabled.
> > > - 3) Only Svadu present in DT => Supervisor must assume Svadu to be
> > > - always enabled.
> > > + 3) Only Svadu present in DT => Supervisor must assume Svadu is
> > > + enabled at boot.
> >
> > Commit message is missing an explanation of why this behaviour change is
> > not problematic. Although, to be honest, I am not sure what the changed text
> > actually means. If only Svadu is present, then the hardware doesn't support
> > Svade, and therefore Svadu would never be anything other than enabled so
> > changing the wording to specify "at boot" seems less clear?
>
> The "enabled at boot" wording came from Andrew's feedback on the previous
> version: "always" is a sensitive term here because ADUE is writable when
> Svadu is implemented, and ADUE=0 behaves as though Svade were implemented.
Whether or not it is writeable, the current wording means that it is not
allowed to be changed. I think that's reasonable because there's nothing
else supported by the hardware so changing it makes no sense.
> Would this wording work?
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next prev parent reply other threads:[~2026-06-10 16:52 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-09 13:00 [PATCH v3 0/3] riscv: support effective hardware PTE A/D updates Yunhui Cui
2026-06-09 13:00 ` [PATCH v3 1/3] dt-bindings: riscv: clarify Svadu boot-time behavior Yunhui Cui
2026-06-09 16:08 ` Conor Dooley
2026-06-10 2:03 ` [External] " yunhui cui
2026-06-10 16:52 ` Conor Dooley [this message]
2026-06-09 13:00 ` [PATCH v3 2/3] riscv: track effective hardware PTE A/D updating Yunhui Cui
2026-06-09 13:16 ` sashiko-bot
2026-06-18 6:16 ` [External] " yunhui cui
2026-06-09 13:00 ` [PATCH v3 3/3] riscv: preserve A/D and soft-dirty state across PTE updates Yunhui Cui
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