Re: [PATCH v3 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The newly introduced `cix,sky1-audss-clock` schema causes a `dt_binding_check` validation failure in the parent `cix,sky1-system-control.yaml` example.
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commit 266331103ef923d7816fb4abbe0e462ec90cdfb6
Author: Joakim Zhang <joakim.zhang@cixtech.com>

dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller

The AUDSS CRU contains an internal clock tree of muxes, dividers and
gates for DSP, I2S, HDA, DMAC and related blocks. The clock provider is
a child node of the cix,sky1-audss-system-control syscon and accesses
registers through the parent MMIO region.

> diff --git a/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml b/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml
> new file mode 100644
> index 0000000000000..dff56f3a425b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/cix,sky1-audss-clock.yaml#

[ ... ]

> +required:
> +  - compatible
> +  - '#clock-cells'
> +  - clocks
> +  - clock-names
> +  - resets
> +  - power-domains

[Severity: Low]
Will this cause a dt_binding_check validation failure in the parent
cix,sky1-system-control.yaml example?

The parent binding contains an incomplete subnode example that will fail
validation against this newly introduced clock schema:

Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml:
        clock-controller {
            compatible = "cix,sky1-audss-clock";
        };

Could the example in cix,sky1-system-control.yaml be updated to include these
newly required properties to prevent validation errors?

> +
> +additionalProperties: false

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Sashiko AI review · https://sashiko.dev/#/patchset/20260610061712.3203984-1-joakim.zhang@cixtech.com?part=3