Re: [PATCH v5 2/4] arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The device tree configuration contradicts the commit message regarding Versa3 output 5.
--

commit ec1059eb98c4c04f3768f67639d5fd666ce6ef3b
Author: John Madieu <john.madieu.xa@bp.renesas.com>

arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator

This patch adds the Renesas 5P35023 (Versa3) programmable clock generator
on the I2C2 bus for the RZ/G3E SMARC EVK. It configures outputs 0 through 4
to provide the necessary reference, audio, and Ethernet clocks.

> diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> index d978619155d24..89428c804efb4 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi

[ ... ]

> @@ -130,6 +136,20 @@ raa215300: pmic@12 {
>  
>  		interrupts-extended = <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING>;
>  	};
> +
> +	versa3: clock-generator@68 {
> +		compatible = "renesas,5p35023";
> +		reg = <0x68>;
> +		#clock-cells = <1>;
> +		clocks = <&x2>;
> +
> +		assigned-clocks = <&versa3 0>, <&versa3 1>,
> +				  <&versa3 2>, <&versa3 3>,
> +				  <&versa3 4>, <&versa3 5>;
> +		assigned-clock-rates = <24000000>, <12288000>,
> +				       <11289600>, <12288000>,
> +				       <25000000>, <25000000>;

[Severity: Medium]
The commit message states "Output 5 (DIFF2) is left out, as it is not
connected on this board."  Is the inclusion of <&versa3 5> in the
assigned-clocks property intentional?

The arrays configure output 5 to 25MHz, which contradicts the commit
message and might unnecessarily enable an unconnected clock output.

> +	};
>  };
>  
>  &i3c {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260610074702.1743334-1-john.madieu.xa@bp.renesas.com?part=2