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From: sashiko-bot@kernel.org
To: "Jishnu Prakash" <jishnu.prakash@oss.qualcomm.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org
Subject: Re: [PATCH v2 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU
Date: Sun, 14 Jun 2026 08:15:45 +0000	[thread overview]
Message-ID: <20260614081546.585941F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260614-adc5_gen3_dt-v2-3-32ec576c5865@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The ADC interrupt handler `adc5_gen3_isr()` may dereference a NULL pointer `adc->handler` if an interrupt fires before the thermal auxiliary driver has registered its event notifier.
--

commit 2afa9a558734cf9fc6ad1120da9026df8390137c
Author: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>

arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU
    
This commit adds ADC nodes for PMM8620AU PMIC instances on the Monaco
platform. It exposes the DIE_TEMP and VPH_PWR channels.

> diff --git a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
> index e990d7367719b..232bcb942b54c 100644
> --- a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
[ ... ]
> @@ -20,6 +21,27 @@ pmm8620au_0_rtc: rtc@6100 {
>  			interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
>  		};
>  
> +		pmm8620au_0_adc: adc@8000 {
> +			compatible = "qcom,spmi-adc5-gen3";
> +			reg = <0x8000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;

[Severity: High]
This is a pre-existing issue, but by enabling the qcom,spmi-adc5-gen3
interrupts here, does this expose a NULL pointer dereference in the
ADC driver's interrupt handler?

In drivers/iio/adc/qcom-spmi-adc5-gen3.c:adc5_gen3_isr(), the handler
checks the device driver state rather than the function pointer:

		adev = adc->tm_aux;
		if (!adev || !adev->dev.driver) {
			dev_err(dev, "adc_tm auxiliary device not initialized\n");
			return IRQ_HANDLED;
		}

		adc->handler(adev);

If an interrupt fires after the driver core sets adev->dev.driver but
before the thermal driver calls adc5_gen3_register_tm_event_notifier()
to set adc->handler, will this result in a kernel panic by dereferencing
a NULL adc->handler?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260614-adc5_gen3_dt-v2-0-32ec576c5865@oss.qualcomm.com?part=3

  reply	other threads:[~2026-06-14  8:15 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-14  8:05 [PATCH v2 0/4] Add ADC support for lemans, monaco and hamoa Jishnu Prakash
2026-06-14  8:05 ` [PATCH v2 1/4] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros Jishnu Prakash
2026-06-14  8:12   ` sashiko-bot
2026-06-14  8:05 ` [PATCH v2 2/4] arm64: dts: qcom: lemans-pmics: Add ADC support for PMM8654au Jishnu Prakash
2026-06-14  8:05 ` [PATCH v2 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU Jishnu Prakash
2026-06-14  8:15   ` sashiko-bot [this message]
2026-06-14  8:05 ` [PATCH v2 4/4] arm64: dts: qcom: hamoa-pmics: Add ADC support Jishnu Prakash
2026-06-14  8:17   ` sashiko-bot

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