* [PATCH v2 1/4] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros
2026-06-14 8:05 [PATCH v2 0/4] Add ADC support for lemans, monaco and hamoa Jishnu Prakash
@ 2026-06-14 8:05 ` Jishnu Prakash
2026-06-14 8:12 ` sashiko-bot
2026-06-14 8:05 ` [PATCH v2 2/4] arm64: dts: qcom: lemans-pmics: Add ADC support for PMM8654au Jishnu Prakash
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Jishnu Prakash @ 2026-06-14 8:05 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Ayyagari Ushasreevalli,
Kamal Wadhwa, Jishnu Prakash
Add macro definitions for virtual channels (combination of ADC channel
number and PMIC SID number), to be used in devicetree by clients of ADC5
GEN3 device and in the "reg" property of ADC channels.
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h | 88 +++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h
new file mode 100644
index 000000000000..aa8e54d7e786
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DTS_ARM64_QCOM_ADC5_GEN3_H__
+#define __DTS_ARM64_QCOM_ADC5_GEN3_H__
+
+/* ADC channels for PMIC5 Gen3 */
+
+#define VIRT_CHAN(sid, chan) ((sid) << 8 | (chan))
+
+#define ADC5_GEN3_REF_GND(sid) VIRT_CHAN(sid, 0x00)
+#define ADC5_GEN3_1P25VREF(sid) VIRT_CHAN(sid, 0x01)
+#define ADC5_GEN3_VREF_VADC(sid) VIRT_CHAN(sid, 0x02)
+#define ADC5_GEN3_DIE_TEMP(sid) VIRT_CHAN(sid, 0x03)
+
+#define ADC5_GEN3_AMUX1_THM(sid) VIRT_CHAN(sid, 0x04)
+#define ADC5_GEN3_AMUX2_THM(sid) VIRT_CHAN(sid, 0x05)
+#define ADC5_GEN3_AMUX3_THM(sid) VIRT_CHAN(sid, 0x06)
+#define ADC5_GEN3_AMUX4_THM(sid) VIRT_CHAN(sid, 0x07)
+#define ADC5_GEN3_AMUX5_THM(sid) VIRT_CHAN(sid, 0x08)
+#define ADC5_GEN3_AMUX6_THM(sid) VIRT_CHAN(sid, 0x09)
+#define ADC5_GEN3_AMUX1_GPIO(sid) VIRT_CHAN(sid, 0x0a)
+#define ADC5_GEN3_AMUX2_GPIO(sid) VIRT_CHAN(sid, 0x0b)
+#define ADC5_GEN3_AMUX3_GPIO(sid) VIRT_CHAN(sid, 0x0c)
+#define ADC5_GEN3_AMUX4_GPIO(sid) VIRT_CHAN(sid, 0x0d)
+
+#define ADC5_GEN3_CHG_TEMP(sid) VIRT_CHAN(sid, 0x10)
+#define ADC5_GEN3_USB_SNS_V_16(sid) VIRT_CHAN(sid, 0x11)
+#define ADC5_GEN3_VIN_DIV16_MUX(sid) VIRT_CHAN(sid, 0x12)
+#define ADC5_GEN3_VREF_BAT_THERM(sid) VIRT_CHAN(sid, 0x15)
+#define ADC5_GEN3_IIN_FB(sid) VIRT_CHAN(sid, 0x17)
+#define ADC5_GEN3_TEMP_ALARM_LITE(sid) VIRT_CHAN(sid, 0x18)
+#define ADC5_GEN3_IIN_SMB(sid) VIRT_CHAN(sid, 0x19)
+#define ADC5_GEN3_ICHG_SMB(sid) VIRT_CHAN(sid, 0x1b)
+#define ADC5_GEN3_ICHG_FB(sid) VIRT_CHAN(sid, 0xa1)
+
+/* 30k pull-up */
+#define ADC5_GEN3_AMUX1_THM_30K_PU(sid) VIRT_CHAN(sid, 0x24)
+#define ADC5_GEN3_AMUX2_THM_30K_PU(sid) VIRT_CHAN(sid, 0x25)
+#define ADC5_GEN3_AMUX3_THM_30K_PU(sid) VIRT_CHAN(sid, 0x26)
+#define ADC5_GEN3_AMUX4_THM_30K_PU(sid) VIRT_CHAN(sid, 0x27)
+#define ADC5_GEN3_AMUX5_THM_30K_PU(sid) VIRT_CHAN(sid, 0x28)
+#define ADC5_GEN3_AMUX6_THM_30K_PU(sid) VIRT_CHAN(sid, 0x29)
+#define ADC5_GEN3_AMUX1_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2a)
+#define ADC5_GEN3_AMUX2_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2b)
+#define ADC5_GEN3_AMUX3_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2c)
+#define ADC5_GEN3_AMUX4_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2d)
+
+/* 100k pull-up */
+#define ADC5_GEN3_AMUX1_THM_100K_PU(sid) VIRT_CHAN(sid, 0x44)
+#define ADC5_GEN3_AMUX2_THM_100K_PU(sid) VIRT_CHAN(sid, 0x45)
+#define ADC5_GEN3_AMUX3_THM_100K_PU(sid) VIRT_CHAN(sid, 0x46)
+#define ADC5_GEN3_AMUX4_THM_100K_PU(sid) VIRT_CHAN(sid, 0x47)
+#define ADC5_GEN3_AMUX5_THM_100K_PU(sid) VIRT_CHAN(sid, 0x48)
+#define ADC5_GEN3_AMUX6_THM_100K_PU(sid) VIRT_CHAN(sid, 0x49)
+#define ADC5_GEN3_AMUX1_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4a)
+#define ADC5_GEN3_AMUX2_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4b)
+#define ADC5_GEN3_AMUX3_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4c)
+#define ADC5_GEN3_AMUX4_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4d)
+
+/* 400k pull-up */
+#define ADC5_GEN3_AMUX1_THM_400K_PU(sid) VIRT_CHAN(sid, 0x64)
+#define ADC5_GEN3_AMUX2_THM_400K_PU(sid) VIRT_CHAN(sid, 0x65)
+#define ADC5_GEN3_AMUX3_THM_400K_PU(sid) VIRT_CHAN(sid, 0x66)
+#define ADC5_GEN3_AMUX4_THM_400K_PU(sid) VIRT_CHAN(sid, 0x67)
+#define ADC5_GEN3_AMUX5_THM_400K_PU(sid) VIRT_CHAN(sid, 0x68)
+#define ADC5_GEN3_AMUX6_THM_400K_PU(sid) VIRT_CHAN(sid, 0x69)
+#define ADC5_GEN3_AMUX1_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6a)
+#define ADC5_GEN3_AMUX2_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6b)
+#define ADC5_GEN3_AMUX3_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6c)
+#define ADC5_GEN3_AMUX4_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6d)
+
+/* 1/3 Divider */
+#define ADC5_GEN3_AMUX1_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8a)
+#define ADC5_GEN3_AMUX2_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8b)
+#define ADC5_GEN3_AMUX3_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8c)
+#define ADC5_GEN3_AMUX4_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8d)
+
+#define ADC5_GEN3_VPH_PWR(sid) VIRT_CHAN(sid, 0x8e)
+#define ADC5_GEN3_VBAT_SNS_QBG(sid) VIRT_CHAN(sid, 0x8f)
+
+#define ADC5_GEN3_VBAT_SNS_CHGR(sid) VIRT_CHAN(sid, 0x94)
+#define ADC5_GEN3_VBAT_2S_MID_QBG(sid) VIRT_CHAN(sid, 0x96)
+#define ADC5_GEN3_VBAT_2S_MID_CHGR(sid) VIRT_CHAN(sid, 0x9d)
+
+#endif /* __DTS_ARM64_QCOM_ADC5_GEN3_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 1/4] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros
2026-06-14 8:05 ` [PATCH v2 1/4] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros Jishnu Prakash
@ 2026-06-14 8:12 ` sashiko-bot
0 siblings, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-06-14 8:12 UTC (permalink / raw)
To: Jishnu Prakash; +Cc: robh, devicetree, conor+dt
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Devicetree binding headers for shared hardware components must be placed in `include/dt-bindings/`, not architecture-specific directories.
--
commit 7bed566fe71218ad2ab3cd2babe147ee1d601536
Author: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros
This commit adds macro definitions for ADC5 Gen3 virtual channels to be
used in devicetrees and ADC channel reg properties.
> diff --git a/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h
> new file mode 100644
> index 0000000000000..aa8e54d7e786a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h
> @@ -0,0 +1,88 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#ifndef __DTS_ARM64_QCOM_ADC5_GEN3_H__
> +#define __DTS_ARM64_QCOM_ADC5_GEN3_H__
> +
> +/* ADC channels for PMIC5 Gen3 */
> +
> +#define VIRT_CHAN(sid, chan) ((sid) << 8 | (chan))
[Severity: Low]
Should this header be placed in include/dt-bindings/ instead of an
architecture-specific directory?
Devicetree binding headers defining ABI constants for reg values typically
reside in include/dt-bindings/ like include/dt-bindings/iio/adc/. Placing
the header in arch/arm64/boot/dts/qcom/ prevents cross-architecture sharing
and can break dt_binding_check validation, as the schema tooling expects to
include these headers from the standard dt-bindings location.
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260614-adc5_gen3_dt-v2-0-32ec576c5865@oss.qualcomm.com?part=1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/4] arm64: dts: qcom: lemans-pmics: Add ADC support for PMM8654au
2026-06-14 8:05 [PATCH v2 0/4] Add ADC support for lemans, monaco and hamoa Jishnu Prakash
2026-06-14 8:05 ` [PATCH v2 1/4] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros Jishnu Prakash
@ 2026-06-14 8:05 ` Jishnu Prakash
2026-06-14 8:05 ` [PATCH v2 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU Jishnu Prakash
2026-06-14 8:05 ` [PATCH v2 4/4] arm64: dts: qcom: hamoa-pmics: Add ADC support Jishnu Prakash
3 siblings, 0 replies; 8+ messages in thread
From: Jishnu Prakash @ 2026-06-14 8:05 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Ayyagari Ushasreevalli,
Kamal Wadhwa, Jishnu Prakash
From: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
Add ADC nodes for the four PMM8654au PMICs (pmm8654au_0 through
pmm8654au_3) on the Lemans platform.
Each ADC node exposes the following ADC channels:
- DIE_TEMP: PMIC die temperature channel
- VPH_PWR: Battery/supply voltage channel
Also add the io-channels and io-channel-names properties under
the temp-alarm nodes so that they can get temperature reading
from the ADC die_temp channels.
Signed-off-by: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans-pmics.dtsi | 93 ++++++++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi
index 341119fc8244..6caec3e4df4b 100644
--- a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/spmi/spmi.h>
+#include "qcom-adc5-gen3.h"
/ {
thermal-zones {
@@ -110,6 +111,8 @@ pmm8654au_0_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmm8654au_0_adc ADC5_GEN3_DIE_TEMP(0)>;
+ io-channel-names = "thermal";
};
pmm8654au_0_pon: pon@1200 {
@@ -141,6 +144,27 @@ pmm8654au_0_rtc: rtc@6100 {
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
};
+ pmm8654au_0_adc: adc@8000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x8000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@3 {
+ reg = <ADC5_GEN3_DIE_TEMP(0)>;
+ label = "pmm8654au_0_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@8e {
+ reg = <ADC5_GEN3_VPH_PWR(0)>;
+ label = "pmm8654au_0_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+ };
+
pmm8654au_0_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
@@ -176,6 +200,29 @@ pmm8654au_1_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmm8654au_1_adc ADC5_GEN3_DIE_TEMP(2)>;
+ io-channel-names = "thermal";
+ };
+
+ pmm8654au_1_adc: adc@8000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x8000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@203 {
+ reg = <ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pmm8654au_1_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@28e {
+ reg = <ADC5_GEN3_VPH_PWR(2)>;
+ label = "pmm8654au_1_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
};
pmm8654au_1_gpios: gpio@8800 {
@@ -200,6 +247,29 @@ pmm8654au_2_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmm8654au_2_adc ADC5_GEN3_DIE_TEMP(4)>;
+ io-channel-names = "thermal";
+ };
+
+ pmm8654au_2_adc: adc@8000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x8000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x4 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@403 {
+ reg = <ADC5_GEN3_DIE_TEMP(4)>;
+ label = "pmm8654au_2_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@48e {
+ reg = <ADC5_GEN3_VPH_PWR(4)>;
+ label = "pmm8654au_2_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
};
pmm8654au_2_gpios: gpio@8800 {
@@ -224,6 +294,29 @@ pmm8654au_3_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmm8654au_3_adc ADC5_GEN3_DIE_TEMP(6)>;
+ io-channel-names = "thermal";
+ };
+
+ pmm8654au_3_adc: adc@8000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x8000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x6 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@603 {
+ reg = <ADC5_GEN3_DIE_TEMP(6)>;
+ label = "pmm8654au_3_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@68e {
+ reg = <ADC5_GEN3_VPH_PWR(6)>;
+ label = "pmm8654au_3_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
};
pmm8654au_3_gpios: gpio@8800 {
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU
2026-06-14 8:05 [PATCH v2 0/4] Add ADC support for lemans, monaco and hamoa Jishnu Prakash
2026-06-14 8:05 ` [PATCH v2 1/4] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros Jishnu Prakash
2026-06-14 8:05 ` [PATCH v2 2/4] arm64: dts: qcom: lemans-pmics: Add ADC support for PMM8654au Jishnu Prakash
@ 2026-06-14 8:05 ` Jishnu Prakash
2026-06-14 8:15 ` sashiko-bot
2026-06-14 8:05 ` [PATCH v2 4/4] arm64: dts: qcom: hamoa-pmics: Add ADC support Jishnu Prakash
3 siblings, 1 reply; 8+ messages in thread
From: Jishnu Prakash @ 2026-06-14 8:05 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Ayyagari Ushasreevalli,
Kamal Wadhwa, Jishnu Prakash
From: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
Add ADC nodes for PMM8620AU PMIC instances (SID 0 and SID 2)
present on the Monaco platform.
Each ADC node exposes the following ADC channels:
- DIE_TEMP: PMIC die temperature channel
- VPH_PWR: Battery/supply voltage channel
Signed-off-by: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/monaco-pmics.dtsi | 43 ++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
index e990d7367719..232bcb942b54 100644
--- a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/spmi/spmi.h>
+#include "qcom-adc5-gen3.h"
&spmi_bus {
pmm8620au_0: pmic@0 {
@@ -20,6 +21,27 @@ pmm8620au_0_rtc: rtc@6100 {
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
};
+ pmm8620au_0_adc: adc@8000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x8000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@3 {
+ reg = <ADC5_GEN3_DIE_TEMP(0)>;
+ label = "pmm8620au_0_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@8e {
+ reg = <ADC5_GEN3_VPH_PWR(0)>;
+ label = "pmm8620au_0_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+ };
+
pmm8620au_0_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
@@ -37,6 +59,27 @@ pmm8650au_1: pmic@2 {
#address-cells = <1>;
#size-cells = <0>;
+ pmm8650au_1_adc: adc@8000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x8000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+
+ channel@203 {
+ reg = <ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pmm8650au_1_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@28e {
+ reg = <ADC5_GEN3_VPH_PWR(2)>;
+ label = "pmm8650au_1_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+ };
+
pmm8650au_1_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU
2026-06-14 8:05 ` [PATCH v2 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU Jishnu Prakash
@ 2026-06-14 8:15 ` sashiko-bot
0 siblings, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-06-14 8:15 UTC (permalink / raw)
To: Jishnu Prakash; +Cc: conor+dt, devicetree, robh
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] The ADC interrupt handler `adc5_gen3_isr()` may dereference a NULL pointer `adc->handler` if an interrupt fires before the thermal auxiliary driver has registered its event notifier.
--
commit 2afa9a558734cf9fc6ad1120da9026df8390137c
Author: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU
This commit adds ADC nodes for PMM8620AU PMIC instances on the Monaco
platform. It exposes the DIE_TEMP and VPH_PWR channels.
> diff --git a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
> index e990d7367719b..232bcb942b54c 100644
> --- a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi
[ ... ]
> @@ -20,6 +21,27 @@ pmm8620au_0_rtc: rtc@6100 {
> interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
> };
>
> + pmm8620au_0_adc: adc@8000 {
> + compatible = "qcom,spmi-adc5-gen3";
> + reg = <0x8000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
[Severity: High]
This is a pre-existing issue, but by enabling the qcom,spmi-adc5-gen3
interrupts here, does this expose a NULL pointer dereference in the
ADC driver's interrupt handler?
In drivers/iio/adc/qcom-spmi-adc5-gen3.c:adc5_gen3_isr(), the handler
checks the device driver state rather than the function pointer:
adev = adc->tm_aux;
if (!adev || !adev->dev.driver) {
dev_err(dev, "adc_tm auxiliary device not initialized\n");
return IRQ_HANDLED;
}
adc->handler(adev);
If an interrupt fires after the driver core sets adev->dev.driver but
before the thermal driver calls adc5_gen3_register_tm_event_notifier()
to set adc->handler, will this result in a kernel panic by dereferencing
a NULL adc->handler?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260614-adc5_gen3_dt-v2-0-32ec576c5865@oss.qualcomm.com?part=3
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 4/4] arm64: dts: qcom: hamoa-pmics: Add ADC support
2026-06-14 8:05 [PATCH v2 0/4] Add ADC support for lemans, monaco and hamoa Jishnu Prakash
` (2 preceding siblings ...)
2026-06-14 8:05 ` [PATCH v2 3/4] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU Jishnu Prakash
@ 2026-06-14 8:05 ` Jishnu Prakash
2026-06-14 8:17 ` sashiko-bot
3 siblings, 1 reply; 8+ messages in thread
From: Jishnu Prakash @ 2026-06-14 8:05 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Ayyagari Ushasreevalli,
Kamal Wadhwa, Jishnu Prakash
From: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
Add ADC node and define channels for:
- Die temperature for PMK8550, PM8550VE* and PMC8380* PMICs.
- PM8550: Die temperature, VPH power, and system thermistors.
Define thermal zones 'sys-0-thermal' through 'sys-6-thermal' which
correspond to the off-PMIC system thermistors connected via
PM8550 AMUX/GPIO lines.
Also,add io-channels and io-channel-names properties to the
temp_alarm nodes so that they can get temperature reading
from the ADC die_temp channels.
Signed-off-by: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi | 250 ++++++++++++++++++++++++++++++
1 file changed, 250 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
index 6a31a0adf8be..2e746ede850f 100644
--- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
@@ -6,7 +6,9 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/spmi/spmi.h>
+#include "qcom-adc5-gen3.h"
/ {
thermal-zones {
@@ -189,6 +191,90 @@ trip1 {
};
};
};
+
+ sys-0-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_GPIO_100K_PU(1)>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ sys-1-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_GPIO_100K_PU(1)>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ sys-2-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ sys-3-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ sys-4-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ sys-5-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ sys-6-thermal {
+ polling-delay-passive = <0>;
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
};
};
@@ -277,6 +363,142 @@ pmk8550_pwm: pwm {
status = "disabled";
};
+
+ pmk8550_vadc: adc@9000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x9000>, <0x9100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
+ #thermal-sensor-cells = <1>;
+ #io-channel-cells = <1>;
+ pinctrl-0 = <&sys_therm_0_gpio3>, <&sys_therm_1_gpio4>;
+ pinctrl-names = "default";
+
+ channel@3 {
+ reg = <ADC5_GEN3_DIE_TEMP(0)>;
+ label = "pmk8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@103 {
+ reg = <ADC5_GEN3_DIE_TEMP(1)>;
+ label = "pm8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@18e {
+ reg = <ADC5_GEN3_VPH_PWR(1)>;
+ label = "pm8550_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ channel@14a {
+ reg = <ADC5_GEN3_AMUX1_GPIO_100K_PU(1)>;
+ label = "pm8550_gpio_01";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@14b {
+ reg = <ADC5_GEN3_AMUX2_GPIO_100K_PU(1)>;
+ label = "pm8550_gpio_02";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@144 {
+ reg = <ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
+ label = "pm8550_therm_2";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@145 {
+ reg = <ADC5_GEN3_AMUX2_THM_100K_PU(1)>;
+ label = "pm8550_therm_3";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@146 {
+ reg = <ADC5_GEN3_AMUX3_THM_100K_PU(1)>;
+ label = "pm8550_therm_4";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@147 {
+ reg = <ADC5_GEN3_AMUX4_THM_100K_PU(1)>;
+ label = "pm8550_therm_5";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@148 {
+ reg = <ADC5_GEN3_AMUX5_THM_100K_PU(1)>;
+ label = "pm8550_therm_6";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@203 {
+ reg = <ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pm8550ve_2_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@303 {
+ reg = <ADC5_GEN3_DIE_TEMP(3)>;
+ label = "pmc8380_3_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@403 {
+ reg = <ADC5_GEN3_DIE_TEMP(4)>;
+ label = "pmc8380_4_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@503 {
+ reg = <ADC5_GEN3_DIE_TEMP(5)>;
+ label = "pmc8380_5_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@603 {
+ reg = <ADC5_GEN3_DIE_TEMP(6)>;
+ label = "pmc8380_6_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@803 {
+ reg = <ADC5_GEN3_DIE_TEMP(8)>;
+ label = "pm8550ve_8_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@903 {
+ reg = <ADC5_GEN3_DIE_TEMP(9)>;
+ label = "pm8550ve_9_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
};
/* PMC8380C */
@@ -291,6 +513,8 @@ pm8550_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>;
+ io-channel-names = "thermal";
};
pm8550_gpios: gpio@8800 {
@@ -301,6 +525,18 @@ pm8550_gpios: gpio@8800 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+
+ sys_therm_0_gpio3: sys-therm_0-gpio3-state {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-high-impedance;
+ };
+
+ sys_therm_1_gpio4: sys-therm-1-gpio4-state {
+ pins = "gpio4";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-high-impedance;
+ };
};
pm8550_flash: led-controller@ee00 {
@@ -329,6 +565,8 @@ pm8550ve_2_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>;
+ io-channel-names = "thermal";
};
pm8550ve_2_gpios: gpio@8800 {
@@ -354,6 +592,8 @@ pmc8380_3_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>;
+ io-channel-names = "thermal";
};
pmc8380_3_gpios: gpio@8800 {
@@ -378,6 +618,8 @@ pmc8380_4_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>;
+ io-channel-names = "thermal";
};
pmc8380_4_gpios: gpio@8800 {
@@ -402,6 +644,8 @@ pmc8380_5_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(5)>;
+ io-channel-names = "thermal";
};
pmc8380_5_gpios: gpio@8800 {
@@ -426,6 +670,8 @@ pmc8380_6_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>;
+ io-channel-names = "thermal";
};
pmc8380_6_gpios: gpio@8800 {
@@ -451,6 +697,8 @@ pm8550ve_8_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(8)>;
+ io-channel-names = "thermal";
};
pm8550ve_8_gpios: gpio@8800 {
@@ -476,6 +724,8 @@ pm8550ve_9_temp_alarm: temp-alarm@a00 {
reg = <0xa00>;
interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(9)>;
+ io-channel-names = "thermal";
};
pm8550ve_9_gpios: gpio@8800 {
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 4/4] arm64: dts: qcom: hamoa-pmics: Add ADC support
2026-06-14 8:05 ` [PATCH v2 4/4] arm64: dts: qcom: hamoa-pmics: Add ADC support Jishnu Prakash
@ 2026-06-14 8:17 ` sashiko-bot
0 siblings, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-06-14 8:17 UTC (permalink / raw)
To: Jishnu Prakash; +Cc: robh, devicetree, conor+dt
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Missing Thermal Sensor Provider for VADC causing thermal zones to indefinitely defer
- [Low] Devicetree Naming Violation: Underscore in node name
--
commit 7b5021a0220835eeee60f0b85faf679ed9b09977
Author: Ayyagari Ushasreevalli <aushasre@qti.qualcomm.com>
arm64: dts: qcom: hamoa-pmics: Add ADC support
This commit adds the ADC node and defines channels for die temperature,
VPH power, and system thermistors for PMK8550, PM8550VE*, and PMC8380*
PMICs. It also defines several thermal zones corresponding to the off-PMIC
system thermistors.
> diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
> index 6a31a0adf8be4..2e746ede850f8 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
[ ... ]
> @@ -189,6 +191,90 @@ trip1 {
> };
> };
> };
> +
> + sys-0-thermal {
> + polling-delay-passive = <0>;
> + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_GPIO_100K_PU(1)>;
[ ... ]
> @@ -277,6 +363,142 @@ pmk8550_pwm: pwm {
>
> status = "disabled";
> };
> +
> + pmk8550_vadc: adc@9000 {
> + compatible = "qcom,spmi-adc5-gen3";
> + reg = <0x9000>, <0x9100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
> + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
> + #thermal-sensor-cells = <1>;
[Severity: Medium]
Does the driver for pmk8550_vadc (qcom-spmi-adc5-gen3.c) actually register a
thermal zone provider?
It looks like the driver currently registers IIO channels but delegates
thermal monitor capabilities to an auxiliary device named adc5_tm_gen3,
which currently has no driver in the kernel to bind to it.
Without a driver registering the thermal zones via
devm_thermal_of_zone_register(), will the generic thermal framework
indefinitely defer probing for these thermal zones, leaving the system
thermistor monitoring uninitialized?
[ ... ]
> @@ -301,6 +525,18 @@ pm8550_gpios: gpio@8800 {
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> +
> + sys_therm_0_gpio3: sys-therm_0-gpio3-state {
[Severity: Low]
This isn't a bug, but does this node name violate devicetree conventions?
Devicetree specifications strongly discourage underscores in node names,
recommending hyphens instead. While the node label (sys_therm_0_gpio3)
can use underscores, should the node name be sys-therm-0-gpio3-state?
The sibling node sys-therm-1-gpio4-state correctly uses hyphens. Leaving
the underscore might trigger a node_name_chars warning in dtc when compiled
with W=1.
> + pins = "gpio3";
> + function = PMIC_GPIO_FUNC_NORMAL;
> + bias-high-impedance;
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260614-adc5_gen3_dt-v2-0-32ec576c5865@oss.qualcomm.com?part=4
^ permalink raw reply [flat|nested] 8+ messages in thread