From: Conor Dooley <conor@kernel.org>
To: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Cc: Lee Jones <lee@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
Min Lin <linmin@eswincomputing.com>,
Yulin Lu <luyulin@eswincomputing.com>,
Samuel Holland <samuel.holland@sifive.com>,
Darshan Prajapati <darshan.prajapati@einfochips.com>,
Pritesh Patel <pritesh.patel@einfochips.com>
Subject: Re: [PATCH 3/7] riscv: dts: eswin: eic7700: add pinctrl support
Date: Mon, 15 Jun 2026 17:33:15 +0100 [thread overview]
Message-ID: <20260615-that-scarf-e048ef152676@spud> (raw)
In-Reply-To: <20260615122016.1110206-4-pinkesh.vaghela@einfochips.com>
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On Mon, Jun 15, 2026 at 05:50:12PM +0530, Pinkesh Vaghela wrote:
> From: Yulin Lu <luyulin@eswincomputing.com>
>
> Add pinctrl node and related pin configuration for EIC7700 SoC
>
> Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
> Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> ---
> .../dts/eswin/eic7700-hifive-premier-p550.dts | 109 +++
> .../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 888 ++++++++++++++++++
> arch/riscv/boot/dts/eswin/eic7700.dtsi | 5 +
> 3 files changed, 1002 insertions(+)
> create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
>
> diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> index 1fb92f0e7c55..e7bb96e14958 100644
> --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> @@ -6,6 +6,7 @@
> /dts-v1/;
>
> #include "eic7700.dtsi"
> +#include "eic7700-pinctrl.dtsi"
>
> / {
> compatible = "sifive,hifive-premier-p550", "eswin,eic7700";
> @@ -18,6 +19,15 @@ aliases {
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + vcc_1v8: vcc1v8 {
Same here.
> + compatible = "regulator-fixed";
> + regulator-name = "vcc1v8";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> };
>
> &xtal {
> @@ -25,6 +35,105 @@ &xtal {
> clock-output-names = "xtal24m";
> };
>
> +&gpio0_pins {
> + bias-disable;
> + input-enable;
> +};
> +
> +&gpio5_pins {
> + bias-disable;
> + input-enable;
> +};
> +
> +&gpio11_pins {
> + bias-disable;
> + input-enable;
> +};
> +
> +&gpio14_pins {
> + bias-pull-up;
> + input-disable;
> +};
> +
> +&gpio15_pins {
> + bias-disable;
> + input-enable;
> +};
> +
> +&gpio28_pins {
> + bias-disable;
> + input-enable;
> +};
> +
> +&gpio43_pins {
> + bias-disable;
> + input-disable;
> +};
> +
> +&gpio71_pins {
> + bias-pull-up;
> + input-disable;
> +};
> +
> +&gpio74_pins {
> + bias-pull-up;
> + input-disable;
> +};
> +
> +&gpio76_pins {
> + bias-disable;
> + input-disable;
> +};
> +
> +&gpio77_pins {
> + bias-pull-up;
> + input-disable;
> +};
> +
> +&gpio79_pins {
> + bias-disable;
> + input-disable;
> +};
> +
> +&gpio80_pins {
> + bias-pull-up;
> + input-disable;
> +};
> +
> +&gpio82_pins {
> + bias-pull-up;
> + input-disable;
> +};
> +
> +&gpio84_pins {
> + bias-disable;
> + input-disable;
> +};
> +
> +&gpio85_pins {
> + bias-pull-up;
> + input-disable;
> +};
> +
> +&gpio94_pins {
> + bias-disable;
> + input-disable;
> +};
> +
> +&gpio106_pins {
> + bias-disable;
> + input-disable;
> +};
> +
> +&gpio111_pins {
> + bias-disable;
> + input-disable;
> +};
> +
> +&pinctrl {
> + vrgmii-supply = <&vcc_1v8>;
> +};
> +
> &uart0 {
> status = "okay";
> };
> diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> new file mode 100644
> index 000000000000..7293df146aa7
> --- /dev/null
> +++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> @@ -0,0 +1,888 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2025 Beijing ESWIN Computing Technology Co., Ltd.
> + *
> + * ESWIN's EIC7700 SoC pin-mux and pin-config options are listed as
> + * device tree nodes in this file.
> + *
> + * Authors: Yulin Lu <luyulin@eswincomputing.com>
> + */
> +
I don't really understand the groups here. I think you should make more
effort to put more pins in each group.
> + gpio1_pins: gpio1-pins {
> + pins = "jtag0_tck";
> + function = "gpio";
> + };
> +
> + gpio2_pins: gpio2-pins {
> + pins = "jtag0_tms";
> + function = "gpio";
> + };
> +
> + gpio3_pins: gpio3-pins {
> + pins = "jtag0_tdi";
> + function = "gpio";
> + };
> +
> + gpio4_pins: gpio4-pins {
> + pins = "jtag0_tdo";
> + function = "gpio";
> + };
Like these 4 for example, why not group these?
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next prev parent reply other threads:[~2026-06-15 16:33 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-15 12:20 [PATCH 0/7] riscv: eswin: eic7700: Add support for clocks, resets, pinctrl, HSP power domain, I2C and watchdog Pinkesh Vaghela
2026-06-15 12:20 ` [PATCH 1/7] riscv: dts: eswin: add reset generator for EIC7700 SoC Pinkesh Vaghela
2026-06-15 12:20 ` [PATCH 2/7] riscv: dts: eswin: add clock " Pinkesh Vaghela
2026-06-15 12:27 ` sashiko-bot
2026-06-15 16:30 ` Conor Dooley
2026-06-15 12:20 ` [PATCH 3/7] riscv: dts: eswin: eic7700: add pinctrl support Pinkesh Vaghela
2026-06-15 12:33 ` sashiko-bot
2026-06-15 16:33 ` Conor Dooley [this message]
2026-06-15 12:20 ` [PATCH 4/7] dt-bindings: mfd: syscon: add ESWIN EIC7700 compatible Pinkesh Vaghela
2026-06-15 16:28 ` Conor Dooley
2026-06-15 12:20 ` [PATCH 5/7] riscv: dts: eswin: add hsp power domain Pinkesh Vaghela
2026-06-15 12:31 ` sashiko-bot
2026-06-15 12:20 ` [PATCH 6/7] riscv: dts: eswin: add I2C controller support Pinkesh Vaghela
2026-06-15 16:35 ` Conor Dooley
2026-06-15 12:20 ` [PATCH 7/7] riscv: dts: eswin: add watchdog support Pinkesh Vaghela
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