Re: [PATCH v8 3/5] iio: adc: versal-sysmon: add I2C driver

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] If a device tree specifies an IRQ for the I2C device, the core driver will register a hardirq handler that calls sleeping I2C regmap functions.
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commit 08d83b16d0694386536f5b4f39bdb131024076df
Author: Salih Erim <salih.erim@amd.com>

iio: adc: versal-sysmon: add I2C driver

This commit adds an I2C transport driver for the Versal SysMon block. It
creates an I2C regmap backend and delegates to devm_versal_sysmon_core_probe()
to initialize the device.

> diff --git a/drivers/iio/adc/versal-sysmon-i2c.c b/drivers/iio/adc/versal-sysmon-i2c.c
> new file mode 100644
> index 0000000000000..cd8d5846ff9b2
> --- /dev/null
> +++ b/drivers/iio/adc/versal-sysmon-i2c.c
[ ... ]
> +static int sysmon_i2c_probe(struct i2c_client *client)
> +{
> +	struct device *dev = &client->dev;
> +	struct regmap *regmap;
> +
> +	regmap = devm_regmap_init(dev, NULL, client, &sysmon_i2c_regmap_config);
> +	if (IS_ERR(regmap))
> +		return PTR_ERR(regmap);
> +
> +	/* I2C has no IRQ connection; events are not supported */
> +	return devm_versal_sysmon_core_probe(dev, regmap);

[Severity: High]
If a device tree incorrectly provides an interrupts property for the I2C
node, will devm_versal_sysmon_core_probe() register an interrupt handler?

Looking at devm_versal_sysmon_core_probe() in versal-sysmon-core.c:

	irq = fwnode_irq_get(dev_fwnode(dev), 0);
	...
	if (irq > 0) {
		...
		ret = sysmon_init_interrupt(sysmon, dev, indio_dev, irq);

If an interrupt is registered, the handler sysmon_iio_irq() will run in
hardirq context, acquire a spinlock, and call regmap_read():

	guard(spinlock)(&sysmon->irq_lock);
	if (regmap_read(sysmon->regmap, SYSMON_ISR, &isr) || ...

Because the I2C regmap backend uses i2c_master_recv() which can sleep,
won't this trigger a sleeping in atomic context panic?

> +}

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Sashiko AI review · https://sashiko.dev/#/patchset/20260616131559.3029543-1-salih.erim@amd.com?part=3