* [PATCH v2 0/2] arm64: dts: renesas: Describe GPU on D3
@ 2026-06-16 17:58 Niklas Söderlund
2026-06-16 17:58 ` [PATCH v2 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE8300 GPU in Renesas R-Car D3 Niklas Söderlund
2026-06-16 17:58 ` [PATCH v2 2/2] arm64: dts: renesas: r8a77995: Add GE8300 GPU node Niklas Söderlund
0 siblings, 2 replies; 6+ messages in thread
From: Niklas Söderlund @ 2026-06-16 17:58 UTC (permalink / raw)
To: Marek Vasut, Geert Uytterhoeven, Conor Dooley, David Airlie,
Frank Binns, Krzysztof Kozlowski, Maarten Lankhorst, Magnus Damm,
Matt Coster, Maxime Ripard, Rob Herring, Simona Vetter,
Thomas Zimmermann, devicetree, dri-devel, linux-renesas-soc
Cc: Niklas Söderlund
Hello,
This series adds the needed bindings to operate the PowerVR GPU on R-Car
D3 SoC.
Together with the D3 clock changes [1] and a still OOT patch for the PVR
driver [2], I'm able to load firmware.
powervr fd000000.gpu: [drm] loaded firmware powervr/rogue_22.67.54.30_v1.fw
powervr fd000000.gpu: [drm] FW version v1.0 (build 6889268 OS)
powervr fd000000.gpu: [drm] Unsupported quirks in firmware image
powervr fd000000.gpu: [drm] Unsupported enhancements in firmware image
powervr fd000000.gpu: [drm] Unsupported features in firmware image
[drm] Initialized powervr 1.0.0 for fd000000.gpu on minor 1
I can run vulkaninfo from mesa (need to add the driver to
pvr_drm_configs):
$ PVR_I_WANT_A_BROKEN_VULKAN_DRIVER=1 meson devenv -C builddir vulkaninfo --summary
WARNING: powervr is not a conformant Vulkan implementation, testing use only.
MESA: warning: Warning: The available RAM is below the minimum required by the Vulkan specification!
MESA: warning: ../src/imagination/vulkan/pvr_border.c:117: FINISHME: Devices without tpu_border_colour_enhanced require entries for compressed formats to be stored in the table pre-compressed.
==========
VULKANINFO
==========
Vulkan Instance Version: 1.4.335
Instance Extensions: count = 20
-------------------------------
VK_EXT_debug_report : extension revision 10
VK_EXT_debug_utils : extension revision 2
VK_EXT_headless_surface : extension revision 1
VK_EXT_surface_maintenance1 : extension revision 1
VK_EXT_swapchain_colorspace : extension revision 5
VK_KHR_device_group_creation : extension revision 1
VK_KHR_display : extension revision 23
VK_KHR_external_fence_capabilities : extension revision 1
VK_KHR_external_memory_capabilities : extension revision 1
VK_KHR_external_semaphore_capabilities : extension revision 1
VK_KHR_get_display_properties2 : extension revision 1
VK_KHR_get_physical_device_properties2 : extension revision 2
VK_KHR_get_surface_capabilities2 : extension revision 1
VK_KHR_portability_enumeration : extension revision 1
VK_KHR_surface : extension revision 25
VK_KHR_surface_protected_capabilities : extension revision 1
VK_KHR_wayland_surface : extension revision 6
VK_KHR_xcb_surface : extension revision 6
VK_KHR_xlib_surface : extension revision 6
VK_LUNARG_direct_driver_loading : extension revision 1
Instance Layers:
----------------
Devices:
========
GPU0:
apiVersion = 1.2.330
driverVersion = 25.99.99
vendorID = 0x1010
deviceID = 0x22054030
deviceType = PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
deviceName = PowerVR Rogue GE8300
driverID = DRIVER_ID_IMAGINATION_OPEN_SOURCE_MESA
driverName = Imagination open-source Mesa driver
driverInfo = Mesa 26.0.0-devel (git-8fb0621f2d)
conformanceVersion = 1.3.8.4
deviceUUID = 19031a08-e22f-9565-d78b-ddda8240380a
driverUUID = 48685174-7bd0-6840-5716-9d00003566aa
GPU1:
apiVersion = 1.4.330
driverVersion = 25.99.99
vendorID = 0x10005
deviceID = 0x0000
deviceType = PHYSICAL_DEVICE_TYPE_CPU
deviceName = llvmpipe (LLVM 21.1.4, 128 bits)
driverID = DRIVER_ID_MESA_LLVMPIPE
driverName = llvmpipe
driverInfo = Mesa 26.0.0-devel (git-8fb0621f2d) (LLVM 21.1.4)
conformanceVersion = 1.3.1.1
deviceUUID = 6d657361-3236-2e30-2e30-2d6465766500
driverUUID = 6c6c766d-7069-7065-5555-494400000000
I can't run test Vulkan applications such as gears as the PVR driver do
not support all features need for GE8300, for example
simple_internal_parameter_format_v1, see [3].
1. https://lore.kernel.org/linux-renesas-soc/20260616175247.2104891-1-niklas.soderlund+renesas@ragnatech.se
2. https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38211#note_3177232
3. https://gitlab.freedesktop.org/imagination/mesa/-/issues/13
Niklas Söderlund (2):
dt-bindings: gpu: img,powervr-rogue: Document GE8300 GPU in Renesas
R-Car D3
arm64: dts: renesas: r8a77995: Add GE8300 GPU node
.../bindings/gpu/img,powervr-rogue.yaml | 14 ++++++++++----
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 15 +++++++++++++++
2 files changed, 25 insertions(+), 4 deletions(-)
--
2.54.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE8300 GPU in Renesas R-Car D3 2026-06-16 17:58 [PATCH v2 0/2] arm64: dts: renesas: Describe GPU on D3 Niklas Söderlund @ 2026-06-16 17:58 ` Niklas Söderlund 2026-06-16 18:05 ` sashiko-bot 2026-06-16 18:28 ` Niklas Söderlund 2026-06-16 17:58 ` [PATCH v2 2/2] arm64: dts: renesas: r8a77995: Add GE8300 GPU node Niklas Söderlund 1 sibling, 2 replies; 6+ messages in thread From: Niklas Söderlund @ 2026-06-16 17:58 UTC (permalink / raw) To: Marek Vasut, Geert Uytterhoeven, Conor Dooley, David Airlie, Frank Binns, Krzysztof Kozlowski, Maarten Lankhorst, Magnus Damm, Matt Coster, Maxime Ripard, Rob Herring, Simona Vetter, Thomas Zimmermann, devicetree, dri-devel, linux-renesas-soc Cc: Niklas Söderlund Document Imagination Technologies PowerVR Rogue GE8300 BNVC 22.67.54.30 present in Renesas R-Car R8A77995 D3 SoCs. Compared to other R-Car Gen3 SoCs the D3 only have one power domain and it is always on. Extend the list of special cases for this to also cover R8A77995 and update the description of it. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- * Changes since v1 - Sort img,img-ge8300 after img,img-ge7800. - Fold special case for power domain into an existing one and update the description. --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index a1f54dbae3f3..b93f49f1fa0a 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -25,6 +25,11 @@ properties: - renesas,r8a779a0-gpu - const: img,img-ge7800 - const: img,img-rogue + - items: + - enum: + - renesas,r8a77995-gpu + - const: img,img-ge8300 + - const: img,img-rogue - items: - enum: - ti,am62-gpu @@ -114,6 +119,7 @@ allOf: contains: enum: - img,img-ge7800 + - img,img-ge8300 - img,img-gx6250 - thead,th1520-gpu then: @@ -159,14 +165,14 @@ allOf: - if: properties: compatible: - contains: - const: thead,th1520-gpu + enum: + - renesas,r8a77995-gpu + - thead,th1520-gpu then: properties: power-domains: items: - - description: The single, unified power domain for the GPU on the - TH1520 SoC, integrating all internal IP power domains. + - description: The single, unified power domain for the GPU. power-domain-names: false required: - power-domains -- 2.54.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE8300 GPU in Renesas R-Car D3 2026-06-16 17:58 ` [PATCH v2 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE8300 GPU in Renesas R-Car D3 Niklas Söderlund @ 2026-06-16 18:05 ` sashiko-bot 2026-06-16 18:28 ` Niklas Söderlund 1 sibling, 0 replies; 6+ messages in thread From: sashiko-bot @ 2026-06-16 18:05 UTC (permalink / raw) To: Niklas Söderlund; +Cc: devicetree, robh, dri-devel, conor+dt, wsa+renesas Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] Incorrect use of `enum:` instead of `contains: enum:` in an `if` block breaks schema matching for `compatible` arrays, bypassing power domain validation. -- commit 911441282d51eed161459bbab16231d9b1fcbca8 Author: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> dt-bindings: gpu: img, powervr-rogue: Document GE8300 GPU in Renesas R-Car D3 This commit documents the GE8300 GPU present in the Renesas R-Car R8A77995 D3 SoCs. It also updates the power domain constraints to account for the D3 having only one power domain that is always on. > diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > index a1f54dbae3f31..b93f49f1fa0a6 100644 > --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml [ ... ] > @@ -159,14 +165,14 @@ allOf: > - if: > properties: > compatible: > - contains: > - const: thead,th1520-gpu > + enum: > + - renesas,r8a77995-gpu > + - thead,th1520-gpu [Severity: Medium] Does this change break the schema matching for these compatible strings? In Device Tree bindings, the compatible property evaluates as an array of strings. Using "enum:" directly on the compatible array checks if the entire array itself equals one of the scalar string values, which will always evaluate to false. Should this use "contains:" along with "enum:"? By dropping the "contains:" keyword during the transition from a single const to an enum, this condition might silently fail to match both the newly added renesas,r8a77995-gpu and the preexisting thead,th1520-gpu strings. This would bypass the power domain validation constraints intended by the block. > then: > properties: > power-domains: > items: > - - description: The single, unified power domain for the GPU on the > - TH1520 SoC, integrating all internal IP power domains. > + - description: The single, unified power domain for the GPU. > power-domain-names: false > required: > - power-domains -- Sashiko AI review · https://sashiko.dev/#/patchset/20260616175835.2109336-1-niklas.soderlund+renesas@ragnatech.se?part=1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE8300 GPU in Renesas R-Car D3 2026-06-16 17:58 ` [PATCH v2 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE8300 GPU in Renesas R-Car D3 Niklas Söderlund 2026-06-16 18:05 ` sashiko-bot @ 2026-06-16 18:28 ` Niklas Söderlund 1 sibling, 0 replies; 6+ messages in thread From: Niklas Söderlund @ 2026-06-16 18:28 UTC (permalink / raw) To: Marek Vasut, Geert Uytterhoeven, Conor Dooley, David Airlie, Frank Binns, Krzysztof Kozlowski, Maarten Lankhorst, Magnus Damm, Matt Coster, Maxime Ripard, Rob Herring, Simona Vetter, Thomas Zimmermann, devicetree, dri-devel, linux-renesas-soc On 2026-06-16 19:58:34 +0200, Niklas Söderlund wrote: > Document Imagination Technologies PowerVR Rogue GE8300 BNVC 22.67.54.30 > present in Renesas R-Car R8A77995 D3 SoCs. > > Compared to other R-Car Gen3 SoCs the D3 only have one power domain and > it is always on. Extend the list of special cases for this to also cover > R8A77995 and update the description of it. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > * Changes since v1 > - Sort img,img-ge8300 after img,img-ge7800. > - Fold special case for power domain into an existing one and update the > description. > --- > .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > index a1f54dbae3f3..b93f49f1fa0a 100644 > --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > @@ -25,6 +25,11 @@ properties: > - renesas,r8a779a0-gpu > - const: img,img-ge7800 > - const: img,img-rogue > + - items: > + - enum: > + - renesas,r8a77995-gpu > + - const: img,img-ge8300 > + - const: img,img-rogue > - items: > - enum: > - ti,am62-gpu > @@ -114,6 +119,7 @@ allOf: > contains: > enum: > - img,img-ge7800 > + - img,img-ge8300 > - img,img-gx6250 > - thead,th1520-gpu > then: > @@ -159,14 +165,14 @@ allOf: > - if: > properties: > compatible: > - contains: The 'contains' node should have been kept, my bad. I wonder why 'make dt_binding_check' or `make dtbs_check' did not catch it. Sorry for the noise. > - const: thead,th1520-gpu > + enum: > + - renesas,r8a77995-gpu > + - thead,th1520-gpu > then: > properties: > power-domains: > items: > - - description: The single, unified power domain for the GPU on the > - TH1520 SoC, integrating all internal IP power domains. > + - description: The single, unified power domain for the GPU. > power-domain-names: false > required: > - power-domains > -- > 2.54.0 > -- Kind Regards, Niklas Söderlund ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] arm64: dts: renesas: r8a77995: Add GE8300 GPU node 2026-06-16 17:58 [PATCH v2 0/2] arm64: dts: renesas: Describe GPU on D3 Niklas Söderlund 2026-06-16 17:58 ` [PATCH v2 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE8300 GPU in Renesas R-Car D3 Niklas Söderlund @ 2026-06-16 17:58 ` Niklas Söderlund 2026-06-16 18:11 ` sashiko-bot 1 sibling, 1 reply; 6+ messages in thread From: Niklas Söderlund @ 2026-06-16 17:58 UTC (permalink / raw) To: Marek Vasut, Geert Uytterhoeven, Conor Dooley, David Airlie, Frank Binns, Krzysztof Kozlowski, Maarten Lankhorst, Magnus Damm, Matt Coster, Maxime Ripard, Rob Herring, Simona Vetter, Thomas Zimmermann, devicetree, dri-devel, linux-renesas-soc Cc: Niklas Söderlund Describe Imagination Technologies PowerVR Rogue GE8300 BNVC 22.67.54.30 present in Renesas R-Car R8A77995 D3 SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> --- * Changes since v1 - Use SPI 119 instead of SPI 223. --- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 5f3fcef7560c..c42d96540ce7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1295,6 +1295,21 @@ gic: interrupt-controller@f1010000 { resets = <&cpg 408>; }; + gpu: gpu@fd000000 { + compatible = "renesas,r8a77995-gpu", + "img,img-ge8300", + "img,img-rogue"; + reg = <0 0xfd000000 0 0x40000>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_CORE R8A77995_CLK_ZG>, + <&cpg CPG_CORE R8A77995_CLK_S3D1>, + <&cpg CPG_MOD 112>; + clock-names = "core", "mem", "sys"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 112>; + status = "disabled"; + }; + vspbs: vsp@fe960000 { compatible = "renesas,vsp2"; reg = <0 0xfe960000 0 0x8000>; -- 2.54.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: renesas: r8a77995: Add GE8300 GPU node 2026-06-16 17:58 ` [PATCH v2 2/2] arm64: dts: renesas: r8a77995: Add GE8300 GPU node Niklas Söderlund @ 2026-06-16 18:11 ` sashiko-bot 0 siblings, 0 replies; 6+ messages in thread From: sashiko-bot @ 2026-06-16 18:11 UTC (permalink / raw) To: Niklas Söderlund; +Cc: conor+dt, dri-devel, devicetree, wsa+renesas, robh Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] The newly added GPU node references core clock R8A77995_CLK_ZG and module clock 112, but neither is implemented in the R8A77995 CPG MSSR clock controller driver. -- commit cb323f9d0762b84aa5d75f999bf135e4920caed4 Author: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> arm64: dts: renesas: r8a77995: Add GE8300 GPU node This commit describes the Imagination Technologies PowerVR Rogue GE8300 GPU node for the Renesas R-Car R8A77995 D3 SoC. > diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi > index 5f3fcef7560cb..c42d96540ce73 100644 > --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi > @@ -1295,6 +1295,21 @@ gic: interrupt-controller@f1010000 { > resets = <&cpg 408>; > }; > > + gpu: gpu@fd000000 { > + compatible = "renesas,r8a77995-gpu", > + "img,img-ge8300", > + "img,img-rogue"; > + reg = <0 0xfd000000 0 0x40000>; > + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_CORE R8A77995_CLK_ZG>, > + <&cpg CPG_CORE R8A77995_CLK_S3D1>, > + <&cpg CPG_MOD 112>; [Severity: Medium] Will this result in a probe failure when the node is enabled by a board? The newly added GPU node requests the core clock R8A77995_CLK_ZG and module clock 112, but neither appears to be defined in the R8A77995 CPG MSSR clock controller driver (drivers/clk/renesas/r8a77995-cpg-mssr.c). If R8A77995_CLK_ZG is missing from r8a77995_core_clks and index 112 is missing from r8a77995_mod_clks, the clock requests will return -ENOENT and prevent the GPU driver from probing successfully. > + clock-names = "core", "mem", "sys"; > + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; > + resets = <&cpg 112>; > + status = "disabled"; > + }; > + [ ... ] -- Sashiko AI review · https://sashiko.dev/#/patchset/20260616175835.2109336-1-niklas.soderlund+renesas@ragnatech.se?part=2 ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-06-16 18:28 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-06-16 17:58 [PATCH v2 0/2] arm64: dts: renesas: Describe GPU on D3 Niklas Söderlund 2026-06-16 17:58 ` [PATCH v2 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE8300 GPU in Renesas R-Car D3 Niklas Söderlund 2026-06-16 18:05 ` sashiko-bot 2026-06-16 18:28 ` Niklas Söderlund 2026-06-16 17:58 ` [PATCH v2 2/2] arm64: dts: renesas: r8a77995: Add GE8300 GPU node Niklas Söderlund 2026-06-16 18:11 ` sashiko-bot
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