* [PATCH v4 1/5] arm64: dts: qcom: pmk8550: add VADC node
2026-06-17 12:53 [PATCH v4 0/5] arm64: dts: qcom: sm8[56]50: add PMIC5 Gen3 ADC channels Neil Armstrong
@ 2026-06-17 12:53 ` Neil Armstrong
2026-06-17 13:02 ` sashiko-bot
2026-06-17 12:53 ` [PATCH v4 2/5] arm64: dts: qcom: sm8550-qrd: add SPMI ADC channels and thermal nodes Neil Armstrong
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Neil Armstrong @ 2026-06-17 12:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong
Add the VADC node and the initial pmk8550 adc channels.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/pmk8550.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi
index 3049eb6b46d7..639c0b1e0c33 100644
--- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
+#include "qcom-adc5-gen3.h"
/ {
reboot-mode {
@@ -44,6 +45,35 @@ pon_resin: resin {
};
};
+ pmk8550_vadc: adc@9000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x9000>, <0x9100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
+
+ channel@0 {
+ reg = <ADC5_GEN3_REF_GND(0)>;
+ label = "pmk8550_offset_ref";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@1 {
+ reg = <ADC5_GEN3_1P25VREF(0)>;
+ label = "pmk8550_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@3 {
+ reg = <ADC5_GEN3_DIE_TEMP(0)>;
+ label = "pmk8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
pmk8550_rtc: rtc@6100 {
compatible = "qcom,pmk8350-rtc";
reg = <0x6100>, <0x6200>;
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v4 1/5] arm64: dts: qcom: pmk8550: add VADC node
2026-06-17 12:53 ` [PATCH v4 1/5] arm64: dts: qcom: pmk8550: add VADC node Neil Armstrong
@ 2026-06-17 13:02 ` sashiko-bot
0 siblings, 0 replies; 11+ messages in thread
From: sashiko-bot @ 2026-06-17 13:02 UTC (permalink / raw)
To: Neil Armstrong; +Cc: devicetree, robh, conor+dt
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The patch includes a nonexistent header file `"qcom-adc5-gen3.h"` and uses undefined parameterized macros, breaking Device Tree compilation.
--
commit 9db08ecceaa2afc05462ac83976c923d21f78ce1
Author: Neil Armstrong <neil.armstrong@linaro.org>
arm64: dts: qcom: pmk8550: add VADC node
This commit adds the VADC node and the initial pmk8550 adc channels.
> diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi
> index 3049eb6b46d7a..639c0b1e0c33a 100644
> --- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/input/linux-event-codes.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/spmi/spmi.h>
> +#include "qcom-adc5-gen3.h"
[Severity: Low]
Is this header missing from the patch? It doesn't appear to be present in
the tree, which causes the C preprocessor to fail with a 'No such file or
directory' error during Device Tree compilation.
[ ... ]
> + pmk8550_vadc: adc@9000 {
> + compatible = "qcom,spmi-adc5-gen3";
> + reg = <0x9000>, <0x9100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
> + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
> + #io-channel-cells = <1>;
> + #thermal-sensor-cells = <1>;
> +
> + channel@0 {
> + reg = <ADC5_GEN3_REF_GND(0)>;
[Severity: Low]
Because the qcom-adc5-gen3.h header is missing, parameterized macros like
ADC5_GEN3_REF_GND remain undefined. Does this lead to dtc syntax errors
when attempting to parse these channel properties?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260617-topic-sm8x50-adc5-gen3-v4-0-4af9251731f1@linaro.org?part=1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v4 2/5] arm64: dts: qcom: sm8550-qrd: add SPMI ADC channels and thermal nodes
2026-06-17 12:53 [PATCH v4 0/5] arm64: dts: qcom: sm8[56]50: add PMIC5 Gen3 ADC channels Neil Armstrong
2026-06-17 12:53 ` [PATCH v4 1/5] arm64: dts: qcom: pmk8550: add VADC node Neil Armstrong
@ 2026-06-17 12:53 ` Neil Armstrong
2026-06-17 13:12 ` sashiko-bot
2026-06-17 12:53 ` [PATCH v4 3/5] arm64: dts: qcom: sm8550-hdk: " Neil Armstrong
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Neil Armstrong @ 2026-06-17 12:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong
Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the
other PMICS on the system.
The thermal nodes are sorted by the sensor channel to be
coherent with the system thermal nodes ordering.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 277 ++++++++++++++++++++++++++++++++
1 file changed, 277 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 2fb2e0be5e4c..9356b40a1850 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -205,6 +205,92 @@ platform {
};
};
+ thermal-zones {
+ skin-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cam-flash-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ wlan-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ rear-tof-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ usb-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(7)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ wls-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX6_THM_100K_PU(7)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@@ -997,27 +1083,218 @@ led@3 {
};
};
+&pm8550_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>;
+ io-channel-names = "thermal";
+};
+
&pm8550b_eusb2_repeater {
vdd18-supply = <&vreg_l15b_1p8>;
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550b_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_c {
status = "okay";
};
+&pm8550vs_c_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_d {
status = "okay";
};
+&pm8550vs_d_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_e {
status = "okay";
};
+&pm8550vs_e_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_g {
status = "okay";
};
+&pm8550vs_g_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>;
+ io-channel-names = "thermal";
+};
+
+&pm8550ve_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>;
+ io-channel-names = "thermal";
+};
+
+&pmk8550_vadc {
+ /* PM8550 Channel nodes */
+ channel@100 {
+ reg = <ADC5_GEN3_REF_GND(1)>;
+ label = "pm8550_offset_ref";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@101 {
+ reg = <ADC5_GEN3_1P25VREF(1)>;
+ label = "pm8550_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@103 {
+ reg = <ADC5_GEN3_DIE_TEMP(1)>;
+ label = "pm8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@144 {
+ reg = <ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
+ label = "pm8550_msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@145 {
+ reg = <ADC5_GEN3_AMUX2_THM_100K_PU(1)>;
+ label = "pm8550_cam_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@146 {
+ reg = <ADC5_GEN3_AMUX3_THM_100K_PU(1)>;
+ label = "pm8550_wlan_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@147 {
+ reg = <ADC5_GEN3_AMUX4_THM_100K_PU(1)>;
+ label = "pm8550_pa_therm_1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@148 {
+ reg = <ADC5_GEN3_AMUX5_THM_100K_PU(1)>;
+ label = "pm8550_rear_tof_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@18e {
+ reg = <ADC5_GEN3_VPH_PWR(1)>;
+ label = "pm8550_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ /* PM8550VS_C Channel nodes */
+ channel@203 {
+ reg = <ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pm8550vs_c_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VS_D Channel nodes */
+ channel@303 {
+ reg = <ADC5_GEN3_DIE_TEMP(3)>;
+ label = "pm8550vs_d_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VS_E Channel nodes */
+ channel@403 {
+ reg = <ADC5_GEN3_DIE_TEMP(4)>;
+ label = "pm8550vs_e_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VE Channel nodes */
+ channel@503 {
+ reg = <ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>;
+ label = "pm8550ve_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VS_G Channel nodes */
+ channel@603 {
+ reg = <ADC5_GEN3_DIE_TEMP(6)>;
+ label = "pm8550vs_g_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550B Channel nodes */
+ channel@700 {
+ reg = <ADC5_GEN3_REF_GND(7)>;
+ label = "pm8550b_offset_ref";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@701 {
+ reg = <ADC5_GEN3_1P25VREF(7)>;
+ label = "pm8550b_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@703 {
+ reg = <ADC5_GEN3_DIE_TEMP(7)>;
+ label = "pm8550b_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@747 {
+ reg = <ADC5_GEN3_AMUX4_THM_100K_PU(7)>;
+ label = "pm8550b_usb_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@749 {
+ reg = <ADC5_GEN3_AMUX6_THM_100K_PU(7)>;
+ label = "pm8550b_wls_therm";
+ qcom,ratiometric;
+ /* use the default settle time */
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@78e {
+ reg = <ADC5_GEN3_VPH_PWR(7)>;
+ label = "pm8550b_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ channel@78f {
+ reg = <ADC5_GEN3_VBAT_SNS_QBG(7)>;
+ label = "pm8550b_vbat_sns_qbg";
+ qcom,pre-scaling = <1 6>;
+ };
+};
+
&pon_pwrkey {
status = "okay";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v4 2/5] arm64: dts: qcom: sm8550-qrd: add SPMI ADC channels and thermal nodes
2026-06-17 12:53 ` [PATCH v4 2/5] arm64: dts: qcom: sm8550-qrd: add SPMI ADC channels and thermal nodes Neil Armstrong
@ 2026-06-17 13:12 ` sashiko-bot
0 siblings, 0 replies; 11+ messages in thread
From: sashiko-bot @ 2026-06-17 13:12 UTC (permalink / raw)
To: Neil Armstrong; +Cc: robh, conor+dt, devicetree
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The patch references missing function-like macros (e.g., `ADC5_GEN3_AMUX1_THM_100K_PU(1)`) and depends on a non-existent header `qcom-adc5-gen3.h`, leading to a dtc syntax error.
--
commit ffba2e8b8d47299d82f0442684ecd38fc3ef60a5
Author: Neil Armstrong <neil.armstrong@linaro.org>
arm64: dts: qcom: sm8550-qrd: add SPMI ADC channels and thermal nodes
This commit adds the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the
other PMICs on the system. It also adds thermal nodes sorted by the
sensor channel to maintain coherency.
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> index 2fb2e0be5e4c6..9356b40a18507 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> @@ -205,6 +205,92 @@ platform {
> };
> };
>
> + thermal-zones {
> + skin-thermal {
> + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
[Severity: Low]
Will this compile correctly?
It appears that ADC5_GEN3_AMUX1_THM_100K_PU and similar macros are being
invoked as function-like macros taking an argument. If the intended header
is missing, the preprocessor might fall back to definitions that do not take
arguments, expanding this to invalid syntax like 0x44(1) and causing a dtc
syntax error.
[ ... ]
> +&pmk8550_vadc {
> + /* PM8550 Channel nodes */
> + channel@100 {
> + reg = <ADC5_GEN3_REF_GND(1)>;
> + label = "pm8550_offset_ref";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + channel@101 {
> + reg = <ADC5_GEN3_1P25VREF(1)>;
> + label = "pm8550_vref_1p25";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + channel@103 {
> + reg = <ADC5_GEN3_DIE_TEMP(1)>;
[Severity: Low]
Are we certain this macro expansion is valid?
Similar to the thermal-sensors property above, using ADC5_GEN3_DIE_TEMP(1)
as a parameterized macro could lead to a syntax error if the available
definitions do not accept arguments.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260617-topic-sm8x50-adc5-gen3-v4-0-4af9251731f1@linaro.org?part=2
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v4 3/5] arm64: dts: qcom: sm8550-hdk: add SPMI ADC channels and thermal nodes
2026-06-17 12:53 [PATCH v4 0/5] arm64: dts: qcom: sm8[56]50: add PMIC5 Gen3 ADC channels Neil Armstrong
2026-06-17 12:53 ` [PATCH v4 1/5] arm64: dts: qcom: pmk8550: add VADC node Neil Armstrong
2026-06-17 12:53 ` [PATCH v4 2/5] arm64: dts: qcom: sm8550-qrd: add SPMI ADC channels and thermal nodes Neil Armstrong
@ 2026-06-17 12:53 ` Neil Armstrong
2026-06-17 15:13 ` sashiko-bot
2026-06-17 12:53 ` [PATCH v4 4/5] arm64: dts: qcom: sm8650-qrd: " Neil Armstrong
2026-06-17 12:53 ` [PATCH v4 5/5] arm64: dts: qcom: sm8650-hdk: " Neil Armstrong
4 siblings, 1 reply; 11+ messages in thread
From: Neil Armstrong @ 2026-06-17 12:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong
Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the
other PMICS on the system.
The thermal nodes are sorted by the sensor channel to be
coherent with the system thermal nodes ordering.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 277 ++++++++++++++++++++++++++++++++
1 file changed, 277 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index ee13e6136a82..f19419f63e36 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -280,6 +280,92 @@ platform {
};
};
+ thermal-zones {
+ skin-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cam-flash-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ wlan-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ rear-tof-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ usb-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(7)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ wls-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX6_THM_100K_PU(7)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+
wcn7850-pmu {
compatible = "qcom,wcn7850-pmu";
@@ -1102,27 +1188,218 @@ led@3 {
};
};
+&pm8550_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>;
+ io-channel-names = "thermal";
+};
+
&pm8550b_eusb2_repeater {
vdd18-supply = <&vreg_l15b_1p8>;
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550b_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_c {
status = "okay";
};
+&pm8550vs_c_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_d {
status = "okay";
};
+&pm8550vs_d_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_e {
status = "okay";
};
+&pm8550vs_e_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_g {
status = "okay";
};
+&pm8550vs_g_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>;
+ io-channel-names = "thermal";
+};
+
+&pm8550ve_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>;
+ io-channel-names = "thermal";
+};
+
+&pmk8550_vadc {
+ /* PM8550 Channel nodes */
+ channel@100 {
+ reg = <ADC5_GEN3_REF_GND(1)>;
+ label = "pm8550_offset_ref";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@101 {
+ reg = <ADC5_GEN3_1P25VREF(1)>;
+ label = "pm8550_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@103 {
+ reg = <ADC5_GEN3_DIE_TEMP(1)>;
+ label = "pm8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@144 {
+ reg = <ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
+ label = "pm8550_msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@145 {
+ reg = <ADC5_GEN3_AMUX2_THM_100K_PU(1)>;
+ label = "pm8550_cam_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@146 {
+ reg = <ADC5_GEN3_AMUX3_THM_100K_PU(1)>;
+ label = "pm8550_wlan_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@147 {
+ reg = <ADC5_GEN3_AMUX4_THM_100K_PU(1)>;
+ label = "pm8550_pa_therm_1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@148 {
+ reg = <ADC5_GEN3_AMUX5_THM_100K_PU(1)>;
+ label = "pm8550_rear_tof_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@18e {
+ reg = <ADC5_GEN3_VPH_PWR(1)>;
+ label = "pm8550_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ /* PM8550VS_C Channel nodes */
+ channel@203 {
+ reg = <ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pm8550vs_c_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VS_D Channel nodes */
+ channel@303 {
+ reg = <ADC5_GEN3_DIE_TEMP(3)>;
+ label = "pm8550vs_d_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VS_E Channel nodes */
+ channel@403 {
+ reg = <ADC5_GEN3_DIE_TEMP(4)>;
+ label = "pm8550vs_e_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VE Channel nodes */
+ channel@503 {
+ reg = <ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>;
+ label = "pm8550ve_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VS_G Channel nodes */
+ channel@603 {
+ reg = <ADC5_GEN3_DIE_TEMP(6)>;
+ label = "pm8550vs_g_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550B Channel nodes */
+ channel@700 {
+ reg = <ADC5_GEN3_REF_GND(7)>;
+ label = "pm8550b_offset_ref";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@701 {
+ reg = <ADC5_GEN3_1P25VREF(7)>;
+ label = "pm8550b_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@703 {
+ reg = <ADC5_GEN3_DIE_TEMP(7)>;
+ label = "pm8550b_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@747 {
+ reg = <ADC5_GEN3_AMUX4_THM_100K_PU(7)>;
+ label = "pm8550b_usb_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@749 {
+ reg = <ADC5_GEN3_AMUX6_THM_100K_PU(7)>;
+ label = "pm8550b_wls_therm";
+ qcom,ratiometric;
+ /* use the default settle time */
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@78e {
+ reg = <ADC5_GEN3_VPH_PWR(7)>;
+ label = "pm8550b_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ channel@78f {
+ reg = <ADC5_GEN3_VBAT_SNS_QBG(7)>;
+ label = "pm8550b_vbat_sns_qbg";
+ qcom,pre-scaling = <1 6>;
+ };
+};
+
&pon_pwrkey {
status = "okay";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v4 3/5] arm64: dts: qcom: sm8550-hdk: add SPMI ADC channels and thermal nodes
2026-06-17 12:53 ` [PATCH v4 3/5] arm64: dts: qcom: sm8550-hdk: " Neil Armstrong
@ 2026-06-17 15:13 ` sashiko-bot
0 siblings, 0 replies; 11+ messages in thread
From: sashiko-bot @ 2026-06-17 15:13 UTC (permalink / raw)
To: Neil Armstrong; +Cc: conor+dt, devicetree, robh
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Device tree compilation fails because the patch uses parameterized macros (e.g., `ADC5_GEN3_DIE_TEMP(1)` and `ADC5_GEN3_AMUX1_THM_100K_PU(1)`) that are undefined. The required local header `qcom-adc5-gen3.h` (included via `#include "qcom-adc5-gen3.h"` in `pmk8550.dtsi` in patch 1 of the series) is completely missing from the tree and was not added by any patch in this series. Furthermore, the similarly named kernel-internal header `include/linux/iio/adc/qcom-adc5-gen3-common.h` defines these as flat integers (e.g., `#define ADC5_GEN3_DIE_TEMP 0x03`), not parameterized macros, so even if included it would cause DTC syntax errors (e.g., `0x03(1)`).
--
commit ab5e68d3e2e92bec8b24c3b38a79b453baff7e21
Author: Neil Armstrong <neil.armstrong@linaro.org>
arm64: dts: qcom: sm8550-hdk: add SPMI ADC channels and thermal nodes
Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS
on the system. The thermal nodes are sorted by the sensor channel to be
coherent with the system thermal nodes ordering.
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> index ee13e6136a825..f19419f63e36b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> @@ -280,6 +280,92 @@ platform {
> };
> };
>
> + thermal-zones {
> + skin-thermal {
> + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
[Severity: Low]
Does this compile? It appears the parameterized macro
ADC5_GEN3_AMUX1_THM_100K_PU(1) is undefined because the required header
is missing from the tree.
[ ... ]
> @@ -1102,27 +1188,218 @@ led@3 {
> };
> };
>
> +&pm8550_temp_alarm {
> + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>;
[Severity: Low]
Similarly here, ADC5_GEN3_DIE_TEMP(1) seems to be missing its definition.
Even if include/linux/iio/adc/qcom-adc5-gen3-common.h were included, it
defines ADC5_GEN3_DIE_TEMP as a flat integer (0x03) rather than a macro
accepting parameters, which would cause a DTC syntax error.
> + io-channel-names = "thermal";
> +};
[ ... ]
> +&pmk8550_vadc {
> + /* PM8550 Channel nodes */
> + channel@100 {
> + reg = <ADC5_GEN3_REF_GND(1)>;
[Severity: Low]
Are these macros defined anywhere in the tree? The ADC channel definitions
throughout this file use these parameterized macros, which appear to rely
on a missing header.
> + label = "pm8550_offset_ref";
> + qcom,pre-scaling = <1 1>;
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260617-topic-sm8x50-adc5-gen3-v4-0-4af9251731f1@linaro.org?part=3
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v4 4/5] arm64: dts: qcom: sm8650-qrd: add SPMI ADC channels and thermal nodes
2026-06-17 12:53 [PATCH v4 0/5] arm64: dts: qcom: sm8[56]50: add PMIC5 Gen3 ADC channels Neil Armstrong
` (2 preceding siblings ...)
2026-06-17 12:53 ` [PATCH v4 3/5] arm64: dts: qcom: sm8550-hdk: " Neil Armstrong
@ 2026-06-17 12:53 ` Neil Armstrong
2026-06-17 13:11 ` sashiko-bot
2026-06-17 12:53 ` [PATCH v4 5/5] arm64: dts: qcom: sm8650-hdk: " Neil Armstrong
4 siblings, 1 reply; 11+ messages in thread
From: Neil Armstrong @ 2026-06-17 12:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong
Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the
other PMICS on the system.
The thermal nodes are sorted by the sensor channel to be
coherent with the system thermal nodes ordering.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 277 ++++++++++++++++++++++++++++++++
1 file changed, 277 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index a3982ae22929..d4a0627ebbf6 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -158,6 +158,92 @@ platform {
};
};
+ thermal-zones {
+ skin-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cam-flash-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ wlan-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ rear-tof-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ usb-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(7)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ wls-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX6_THM_100K_PU(7)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
@@ -1040,27 +1126,218 @@ led@3 {
};
};
+&pm8550_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>;
+ io-channel-names = "thermal";
+};
+
&pm8550b_eusb2_repeater {
vdd18-supply = <&vreg_l15b_1p8>;
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550b_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_c {
status = "okay";
};
+&pm8550vs_c_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_d {
status = "okay";
};
+&pm8550vs_d_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_e {
status = "okay";
};
+&pm8550vs_e_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_g {
status = "okay";
};
+&pm8550vs_g_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>;
+ io-channel-names = "thermal";
+};
+
+&pm8550ve_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>;
+ io-channel-names = "thermal";
+};
+
+&pmk8550_vadc {
+ /* PM8550 Channel nodes */
+ channel@100 {
+ reg = <ADC5_GEN3_REF_GND(1)>;
+ label = "pm8550_offset_ref";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@101 {
+ reg = <ADC5_GEN3_1P25VREF(1)>;
+ label = "pm8550_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@103 {
+ reg = <ADC5_GEN3_DIE_TEMP(1)>;
+ label = "pm8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@144 {
+ reg = <ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
+ label = "pm8550_msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@145 {
+ reg = <ADC5_GEN3_AMUX2_THM_100K_PU(1)>;
+ label = "pm8550_cam_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@146 {
+ reg = <ADC5_GEN3_AMUX3_THM_100K_PU(1)>;
+ label = "pm8550_wlan_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@147 {
+ reg = <ADC5_GEN3_AMUX4_THM_100K_PU(1)>;
+ label = "pm8550_pa_therm_1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@148 {
+ reg = <ADC5_GEN3_AMUX5_THM_100K_PU(1)>;
+ label = "pm8550_rear_tof_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@18e {
+ reg = <ADC5_GEN3_VPH_PWR(1)>;
+ label = "pm8550_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ /* PM8550VS_C Channel nodes */
+ channel@203 {
+ reg = <ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pm8550vs_c_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VS_D Channel nodes */
+ channel@303 {
+ reg = <ADC5_GEN3_DIE_TEMP(3)>;
+ label = "pm8550vs_d_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VS_E Channel nodes */
+ channel@403 {
+ reg = <ADC5_GEN3_DIE_TEMP(4)>;
+ label = "pm8550vs_e_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VE Channel nodes */
+ channel@503 {
+ reg = <ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>;
+ label = "pm8550ve_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VS_G Channel nodes */
+ channel@603 {
+ reg = <ADC5_GEN3_DIE_TEMP(6)>;
+ label = "pm8550vs_g_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550B Channel nodes */
+ channel@700 {
+ reg = <ADC5_GEN3_REF_GND(7)>;
+ label = "pm8550b_offset_ref";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@701 {
+ reg = <ADC5_GEN3_1P25VREF(7)>;
+ label = "pm8550b_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@703 {
+ reg = <ADC5_GEN3_DIE_TEMP(7)>;
+ label = "pm8550b_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@747 {
+ reg = <ADC5_GEN3_AMUX4_THM_100K_PU(7)>;
+ label = "pm8550b_usb_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@749 {
+ reg = <ADC5_GEN3_AMUX6_THM_100K_PU(7)>;
+ label = "pm8550b_wls_therm";
+ qcom,ratiometric;
+ /* use the default settle time */
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@78e {
+ reg = <ADC5_GEN3_VPH_PWR(7)>;
+ label = "pm8550b_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ channel@78f {
+ reg = <ADC5_GEN3_VBAT_SNS_QBG(7)>;
+ label = "pm8550b_vbat_sns_qbg";
+ qcom,pre-scaling = <1 6>;
+ };
+};
+
&qup_i2c3_data_clk {
/* Use internal I2C pull-up */
bias-pull-up = <2200>;
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v4 4/5] arm64: dts: qcom: sm8650-qrd: add SPMI ADC channels and thermal nodes
2026-06-17 12:53 ` [PATCH v4 4/5] arm64: dts: qcom: sm8650-qrd: " Neil Armstrong
@ 2026-06-17 13:11 ` sashiko-bot
0 siblings, 0 replies; 11+ messages in thread
From: sashiko-bot @ 2026-06-17 13:11 UTC (permalink / raw)
To: Neil Armstrong; +Cc: devicetree, conor+dt, robh
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The patch relies on undefined parameterized macros (e.g., `ADC5_GEN3_DIE_TEMP(1)`), which will completely break device tree compilation.
- [Low] The unit-address of the PM8550VE thermal channel node (`channel@503`) does not match its evaluated `reg` property (`0x803`), causing a DTC unit_address_vs_reg warning.
--
commit 3ff480d3d3bffdbe30ed6468b6ac6d09de994eeb
Author: Neil Armstrong <neil.armstrong@linaro.org>
arm64: dts: qcom: sm8650-qrd: add SPMI ADC channels and thermal nodes
Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the
other PMICS on the system. The thermal nodes are sorted by the
sensor channel to be coherent with the system thermal nodes ordering.
> diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
> index a3982ae229290..d4a0627ebbf6e 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
> @@ -158,6 +158,92 @@ platform {
> };
> };
>
> + thermal-zones {
> + skin-thermal {
> + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
[Severity: Low]
Will this cause a device tree compilation failure?
It appears this patch uses parameterized macros like
ADC5_GEN3_AMUX1_THM_100K_PU(1) and ADC5_GEN3_DIE_TEMP(1), but the required
header defining them (qcom-adc5-gen3.h) isn't present in the tree.
The existing qcom-adc5-gen3-common.h defines these macros without arguments
(e.g., ADC5_GEN3_DIE_TEMP is 0x03), so using them with parameters will
evaluate to a syntax error like 0x03(1).
[ ... ]
> + /* PM8550VE Channel nodes */
> + channel@503 {
> + reg = <ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>;
[Severity: Low]
Does this unit-address match the evaluated reg property?
PMK8550VE_SID evaluates to 8 in sm8650-qrd.dts. Assuming the macro calculates
the address using the SID, the reg property will logically evaluate to 0x803.
The hardcoded channel@503 unit-address would then mismatch the 0x803 reg
property, which will trigger a DTC unit_address_vs_reg warning once the build
failure is resolved. Should this node be named channel@803?
> + label = "pm8550ve_die_temp";
> + qcom,pre-scaling = <1 1>;
> + };
> +
> + /* PM8550VS_G Channel nodes */
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260617-topic-sm8x50-adc5-gen3-v4-0-4af9251731f1@linaro.org?part=4
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v4 5/5] arm64: dts: qcom: sm8650-hdk: add SPMI ADC channels and thermal nodes
2026-06-17 12:53 [PATCH v4 0/5] arm64: dts: qcom: sm8[56]50: add PMIC5 Gen3 ADC channels Neil Armstrong
` (3 preceding siblings ...)
2026-06-17 12:53 ` [PATCH v4 4/5] arm64: dts: qcom: sm8650-qrd: " Neil Armstrong
@ 2026-06-17 12:53 ` Neil Armstrong
2026-06-17 13:30 ` sashiko-bot
4 siblings, 1 reply; 11+ messages in thread
From: Neil Armstrong @ 2026-06-17 12:53 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong
Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the
other PMICS on the system.
The thermal nodes are sorted by the sensor channel to be
coherent with the system thermal nodes ordering.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 277 ++++++++++++++++++++++++++++++++
1 file changed, 277 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
index eabc828c05b4..05af2913055e 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -220,6 +220,92 @@ platform {
};
};
+ thermal-zones {
+ skin-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cam-flash-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ wlan-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ rear-tof-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ usb-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(7)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ wls-thermal {
+ thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX6_THM_100K_PU(7)>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
@@ -1041,27 +1127,218 @@ led@3 {
};
};
+&pm8550_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>;
+ io-channel-names = "thermal";
+};
+
&pm8550b_eusb2_repeater {
vdd18-supply = <&vreg_l15b_1p8>;
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550b_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_c {
status = "okay";
};
+&pm8550vs_c_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_d {
status = "okay";
};
+&pm8550vs_d_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_e {
status = "okay";
};
+&pm8550vs_e_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>;
+ io-channel-names = "thermal";
+};
+
&pm8550vs_g {
status = "okay";
};
+&pm8550vs_g_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>;
+ io-channel-names = "thermal";
+};
+
+&pm8550ve_temp_alarm {
+ io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>;
+ io-channel-names = "thermal";
+};
+
+&pmk8550_vadc {
+ /* PM8550 Channel nodes */
+ channel@100 {
+ reg = <ADC5_GEN3_REF_GND(1)>;
+ label = "pm8550_offset_ref";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@101 {
+ reg = <ADC5_GEN3_1P25VREF(1)>;
+ label = "pm8550_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@103 {
+ reg = <ADC5_GEN3_DIE_TEMP(1)>;
+ label = "pm8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@144 {
+ reg = <ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
+ label = "pm8550_msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@145 {
+ reg = <ADC5_GEN3_AMUX2_THM_100K_PU(1)>;
+ label = "pm8550_cam_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@146 {
+ reg = <ADC5_GEN3_AMUX3_THM_100K_PU(1)>;
+ label = "pm8550_wlan_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@147 {
+ reg = <ADC5_GEN3_AMUX4_THM_100K_PU(1)>;
+ label = "pm8550_pa_therm_1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@148 {
+ reg = <ADC5_GEN3_AMUX5_THM_100K_PU(1)>;
+ label = "pm8550_rear_tof_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@18e {
+ reg = <ADC5_GEN3_VPH_PWR(1)>;
+ label = "pm8550_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ /* PM8550VS_C Channel nodes */
+ channel@203 {
+ reg = <ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pm8550vs_c_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VS_D Channel nodes */
+ channel@303 {
+ reg = <ADC5_GEN3_DIE_TEMP(3)>;
+ label = "pm8550vs_d_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VS_E Channel nodes */
+ channel@403 {
+ reg = <ADC5_GEN3_DIE_TEMP(4)>;
+ label = "pm8550vs_e_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VE Channel nodes */
+ channel@503 {
+ reg = <ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>;
+ label = "pm8550ve_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550VS_G Channel nodes */
+ channel@603 {
+ reg = <ADC5_GEN3_DIE_TEMP(6)>;
+ label = "pm8550vs_g_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550B Channel nodes */
+ channel@700 {
+ reg = <ADC5_GEN3_REF_GND(7)>;
+ label = "pm8550b_offset_ref";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@701 {
+ reg = <ADC5_GEN3_1P25VREF(7)>;
+ label = "pm8550b_vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@703 {
+ reg = <ADC5_GEN3_DIE_TEMP(7)>;
+ label = "pm8550b_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@747 {
+ reg = <ADC5_GEN3_AMUX4_THM_100K_PU(7)>;
+ label = "pm8550b_usb_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@749 {
+ reg = <ADC5_GEN3_AMUX6_THM_100K_PU(7)>;
+ label = "pm8550b_wls_therm";
+ qcom,ratiometric;
+ /* use the default settle time */
+ qcom,pre-scaling = <1 1>;
+ qcom,adc-tm;
+ };
+
+ channel@78e {
+ reg = <ADC5_GEN3_VPH_PWR(7)>;
+ label = "pm8550b_vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ channel@78f {
+ reg = <ADC5_GEN3_VBAT_SNS_QBG(7)>;
+ label = "pm8550b_vbat_sns_qbg";
+ qcom,pre-scaling = <1 6>;
+ };
+};
+
&pon_pwrkey {
status = "okay";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v4 5/5] arm64: dts: qcom: sm8650-hdk: add SPMI ADC channels and thermal nodes
2026-06-17 12:53 ` [PATCH v4 5/5] arm64: dts: qcom: sm8650-hdk: " Neil Armstrong
@ 2026-06-17 13:30 ` sashiko-bot
0 siblings, 0 replies; 11+ messages in thread
From: sashiko-bot @ 2026-06-17 13:30 UTC (permalink / raw)
To: Neil Armstrong; +Cc: robh, devicetree, conor+dt
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Dangerously high and ineffective passive trip points for skin and ambient thermal zones.
- [Low] Use of undefined macro ADC5_GEN3_DIE_TEMP(x) causes a DTC syntax error.
- [Low] The unit-address of the pm8550ve_die_temp ADC channel node does not match its reg property.
--
commit f0b9d1fd765aad624439c8e56ebe37c1e26e52c9
Author: Neil Armstrong <neil.armstrong@linaro.org>
arm64: dts: qcom: sm8650-hdk: add SPMI ADC channels and thermal nodes
Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the
other PMICS on the system.
> diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
> index eabc828c05b4c..05af2913055ed 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
> @@ -220,6 +220,92 @@ platform {
> };
> };
>
> + thermal-zones {
> + skin-thermal {
> + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>;
[Severity: Low]
Is the header defining parameterized macros like ADC5_GEN3_AMUX1_THM_100K_PU(x)
missing? Without it, the C preprocessor leaves the macro unexpanded, or expands
the parameterless constant in include/linux/iio/adc/qcom-adc5-gen3-common.h to
0x03(1), which causes a DTC syntax error and breaks the build.
> +
> + trips {
> + active-config0 {
> + temperature = <125000>;
> + hysteresis = <1000>;
> + type = "passive";
> + };
[Severity: High]
Is it intentional to set the passive trip point for the skin-thermal zone to
125°C? While 125°C is a typical critical threshold for internal silicon dies,
it is physically impossible for skin or external surface temperatures without
causing severe burns or melting the device. Does this functionally disable
skin thermal mitigation?
[ ... ]
> @@ -1041,27 +1127,218 @@ led@3 {
> };
> };
[ ... ]
> + /* PM8550VE Channel nodes */
> + channel@503 {
> + reg = <ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>;
> + label = "pm8550ve_die_temp";
[Severity: Low]
Does the unit-address channel@503 match the evaluated reg property here?
Assuming PMK8550VE_SID is 8, the standard SPMI ADC encoding (sid << 8 | offset)
would evaluate to 0x803, making the unit-address channel@503 mismatched.
Should this be updated to channel@803 to avoid dtc validation warnings?
> + qcom,pre-scaling = <1 1>;
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260617-topic-sm8x50-adc5-gen3-v4-0-4af9251731f1@linaro.org?part=5
^ permalink raw reply [flat|nested] 11+ messages in thread