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From: sashiko-bot@kernel.org
To: Biju <biju.das.au@gmail.com>
Cc: robh@kernel.org, conor+dt@kernel.org,
	wsa+renesas@sang-engineering.com, devicetree@vger.kernel.org
Subject: Re: [PATCH v18 01/12] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC
Date: Mon, 22 Jun 2026 16:05:47 +0000	[thread overview]
Message-ID: <20260622160548.04F5B1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260622155610.184271-2-biju.das.jz@bp.renesas.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Relaxing the global `maxItems` for `resets` and `reset-names` from 1 to 3 removes the strict constraint for legacy controllers, allowing them to incorrectly define up to 3 resets.
--

commit 5bd955e3c9833c72a7847cd9926c293d95e5c927
Author: Biju Das <biju.das.jz@bp.renesas.com>

dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC

Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI
controller is similar to RZ/G2L but has five clocks (core, clkh,
cd, aclk, aclkm) and three resets (rst, axim, axis), so update the
clocks/clock-names maximum to 5 and resets/reset-names maximum to 3.
It has an internal divider for all modes except HS400, and a 2048-bit
divider compared to 512 on others.

> diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> @@ -116,7 +117,12 @@ properties:
>      maxItems: 1
>  
>    resets:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 3
> +
> +  reset-names:
> +    minItems: 1
> +    maxItems: 3

[ ... ]

> @@ -155,60 +161,101 @@ allOf:
[ ... ]
> +        else:
> +          if:
> +            properties:
> +              compatible:
> +                contains:
> +                  enum:
> +                    - renesas,rcar-gen2-sdhi
> +                    - renesas,rcar-gen3-sdhi
> +                    - renesas,rcar-gen4-sdhi
> +          then:
> +            properties:
> +              clocks:
> +                minItems: 1
> +                maxItems: 3
> +              clock-names:
> +                minItems: 1
> +                uniqueItems: true
> +                items:
> +                  - const: core
> +                  - enum: [ clkh, cd ]
> +                  - const: cd
> +          else:
> +            properties:
> +              clocks:
> +                minItems: 1
> +                maxItems: 2
> +              clock-names:
> +                minItems: 1
> +                items:
> +                  - const: core
> +                  - const: cd

[Severity: Medium]
Since the top-level resets and reset-names maxItems were increased to 3, do
the conditional branches for R-Car Gen2/3/4 and the subsequent fallback branch
need to explicitly constrain resets and reset-names back to maxItems: 1?

Without overriding the top-level relaxation here, it appears legacy controllers
are now permitted to incorrectly define up to 3 resets.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260622155610.184271-1-biju.das.jz@bp.renesas.com?part=1

      reply	other threads:[~2026-06-22 16:05 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-22 15:55 [PATCH v18 00/12] Add Renesas RZ/G3L SD/eMMC support Biju
2026-06-22 15:55 ` [PATCH v18 01/12] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC Biju
2026-06-22 16:05   ` sashiko-bot [this message]

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