* [PATCH v18 00/12] Add Renesas RZ/G3L SD/eMMC support
@ 2026-06-22 15:55 Biju
2026-06-22 15:55 ` [PATCH v18 01/12] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC Biju
0 siblings, 1 reply; 3+ messages in thread
From: Biju @ 2026-06-22 15:55 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Philipp Zabel, Magnus Damm
Cc: Biju Das, Wolfram Sang, linux-mmc, devicetree, linux-kernel,
linux-renesas-soc, Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G3L SoC has:
Channel 0 supports SD and eMMC (including HS400/HS400ES).
Channel 1 supports SD and eMMC (except for HS400).
Channel 2 supports SD.
The SoC supports a maximum frequency of 150 MHz. The SD0 interface does
not support IOVS and PWEN in the SDHI register (no internal regulator),
unlike SD1 and SD2. It has an internal divider for all modes except HS400.
It also has a 2048-bit divider compared to 512 on others. Moreover
RZ/G3L supports HS400 enhanced strobe mode.
v17->v18:
* Collected tag
* Merged patch #4 and #5 and updated commit description
* Annotated the empty sentinel entries in the OF match tables with a
"Sentinel." comment for clarity.
* Retained the tag as it is a trivial cleanup.
* New patches drop struct renesas_sdhi_hw_info, instead using
renesas_sdhi_of_data and tmio_mmc_data.
* Dropped clk, pinctrl, SoC, and board dtsi from this patch series;
will send later.
v1->v17:
* Collected tag for binding patch.
* Resending the series as there is an issue with patch threading from
patch #14.
Biju Das (12):
dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC
mmc: renesas_sdhi: Fix whitespace alignment in struct
renesas_sdhi_of_data
mmc: renesas_sdhi: Add clk_mask field to support SoC-specific clock
divider widths
mmc: renesas_sdhi: Add max_divider field to support SoC-specific clock
divider ranges
mmc: renesas_sdhi: Add tuning delay support for RZ/G2L
mmc: renesas_sdhi: Add TMIO_MMC_INTERNAL_DIVIDER flag
mmc: renesas_sdhi: Add optional axis/axim reset controls
mmc: renesas_sdhi: Add RZ/G3L SDHI support
mmc: renesas_sdhi: Save and restore IOVS across suspend/resume
mmc: renesas_sdhi: Make HS400 OSEL bit configurable per SoC
mmc: renesas_sdhi: Add RZ/G3L HS400 support
mmc: renesas_sdhi: Add HS400 enhanced strobe support for RZ/G3L
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 101 ++++++--
drivers/mmc/host/renesas_sdhi.h | 12 +-
drivers/mmc/host/renesas_sdhi_core.c | 239 ++++++++++++++----
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 73 +++++-
drivers/mmc/host/renesas_sdhi_sys_dmac.c | 12 +-
include/linux/platform_data/tmio.h | 18 ++
6 files changed, 370 insertions(+), 85 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH v18 01/12] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC 2026-06-22 15:55 [PATCH v18 00/12] Add Renesas RZ/G3L SD/eMMC support Biju @ 2026-06-22 15:55 ` Biju 2026-06-22 16:05 ` sashiko-bot 0 siblings, 1 reply; 3+ messages in thread From: Biju @ 2026-06-22 15:55 UTC (permalink / raw) To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven, Magnus Damm Cc: Biju Das, Wolfram Sang, linux-mmc, devicetree, linux-kernel, linux-renesas-soc, Prabhakar Mahadev Lad, Biju Das, Conor Dooley From: Biju Das <biju.das.jz@bp.renesas.com> Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI controller is similar to RZ/G2L but has five clocks (core, clkh, cd, aclk, aclkm) and three resets (rst, axim, axis), so update the clocks/clock-names maximum to 5 and resets/reset-names maximum to 3. It has an internal divider for all modes except HS400, and a 2048-bit divider compared to 512 on others. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v17->v18: * No change. v1->v17: * Collected tag. --- .../devicetree/bindings/mmc/renesas,sdhi.yaml | 101 +++++++++++++----- 1 file changed, 75 insertions(+), 26 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 4d66966ce290..16cb395403f6 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -18,6 +18,7 @@ properties: - renesas,sdhi-r7s9210 # SH-Mobile AG5 - renesas,sdhi-r8a73a4 # R-Mobile APE6 - renesas,sdhi-r8a7740 # R-Mobile A1 + - renesas,sdhi-r9a08g046 # RZ/G3L - renesas,sdhi-r9a09g057 # RZ/V2H(P) - renesas,sdhi-sh73a0 # R-Mobile APE6 - items: @@ -86,11 +87,11 @@ properties: clocks: minItems: 1 - maxItems: 4 + maxItems: 5 clock-names: minItems: 1 - maxItems: 4 + maxItems: 5 dmas: minItems: 4 @@ -116,7 +117,12 @@ properties: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + maxItems: 3 + + reset-names: + minItems: 1 + maxItems: 3 pinctrl-0: minItems: 1 @@ -155,60 +161,101 @@ allOf: properties: compatible: contains: - enum: - - renesas,sdhi-r9a09g057 - - renesas,rzg2l-sdhi + const: renesas,sdhi-r9a08g046 then: properties: clocks: items: - description: IMCLK, SDHI channel main clock1. - description: CLK_HS, SDHI channel High speed clock which operates - 4 times that of SDHI channel main clock1. + 2 times that of SDHI channel main clock1. - description: IMCLK2, SDHI channel main clock2. When this clock is turned off, external SD card detection cannot be detected. - - description: ACLK, SDHI channel bus clock. + - description: ACLK/IACLKS, SDHI channel bus clock. + - description: IACLKM, SDHI channel bus clock m. clock-names: items: - const: core - const: clkh - const: cd - const: aclk + - const: aclkm + resets: + items: + - description: rst, Core reset. + - description: axim, SDHI axi bus reset m. + - description: axis, SDHI axi bus reset s. + reset-names: + items: + - const: rst + - const: axim + - const: axis required: - clock-names - resets + - reset-names else: if: properties: compatible: contains: enum: - - renesas,rcar-gen2-sdhi - - renesas,rcar-gen3-sdhi - - renesas,rcar-gen4-sdhi + - renesas,sdhi-r9a09g057 + - renesas,rzg2l-sdhi then: properties: clocks: - minItems: 1 - maxItems: 3 - clock-names: - minItems: 1 - uniqueItems: true items: - - const: core - - enum: [ clkh, cd ] - - const: cd - else: - properties: - clocks: - minItems: 1 - maxItems: 2 + - description: IMCLK, SDHI channel main clock1. + - description: CLK_HS, SDHI channel High speed clock which operates + 4 times that of SDHI channel main clock1. + - description: IMCLK2, SDHI channel main clock2. When this clock is + turned off, external SD card detection cannot be + detected. + - description: ACLK, SDHI channel bus clock. clock-names: - minItems: 1 items: - const: core + - const: clkh - const: cd + - const: aclk + resets: + maxItems: 1 + required: + - clock-names + - resets + else: + if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-sdhi + - renesas,rcar-gen3-sdhi + - renesas,rcar-gen4-sdhi + then: + properties: + clocks: + minItems: 1 + maxItems: 3 + clock-names: + minItems: 1 + uniqueItems: true + items: + - const: core + - enum: [ clkh, cd ] + - const: cd + else: + properties: + clocks: + minItems: 1 + maxItems: 2 + clock-names: + minItems: 1 + items: + - const: core + - const: cd - if: properties: @@ -247,7 +294,9 @@ allOf: properties: compatible: contains: - const: renesas,sdhi-r9a09g057 + enum: + - renesas,sdhi-r9a08g046 + - renesas,sdhi-r9a09g057 then: properties: vqmmc-regulator: -- 2.43.0 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v18 01/12] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC 2026-06-22 15:55 ` [PATCH v18 01/12] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC Biju @ 2026-06-22 16:05 ` sashiko-bot 0 siblings, 0 replies; 3+ messages in thread From: sashiko-bot @ 2026-06-22 16:05 UTC (permalink / raw) To: Biju; +Cc: robh, conor+dt, wsa+renesas, devicetree Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] Relaxing the global `maxItems` for `resets` and `reset-names` from 1 to 3 removes the strict constraint for legacy controllers, allowing them to incorrectly define up to 3 resets. -- commit 5bd955e3c9833c72a7847cd9926c293d95e5c927 Author: Biju Das <biju.das.jz@bp.renesas.com> dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI controller is similar to RZ/G2L but has five clocks (core, clkh, cd, aclk, aclkm) and three resets (rst, axim, axis), so update the clocks/clock-names maximum to 5 and resets/reset-names maximum to 3. It has an internal divider for all modes except HS400, and a 2048-bit divider compared to 512 on others. > diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml > --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml > +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml > @@ -116,7 +117,12 @@ properties: > maxItems: 1 > > resets: > - maxItems: 1 > + minItems: 1 > + maxItems: 3 > + > + reset-names: > + minItems: 1 > + maxItems: 3 [ ... ] > @@ -155,60 +161,101 @@ allOf: [ ... ] > + else: > + if: > + properties: > + compatible: > + contains: > + enum: > + - renesas,rcar-gen2-sdhi > + - renesas,rcar-gen3-sdhi > + - renesas,rcar-gen4-sdhi > + then: > + properties: > + clocks: > + minItems: 1 > + maxItems: 3 > + clock-names: > + minItems: 1 > + uniqueItems: true > + items: > + - const: core > + - enum: [ clkh, cd ] > + - const: cd > + else: > + properties: > + clocks: > + minItems: 1 > + maxItems: 2 > + clock-names: > + minItems: 1 > + items: > + - const: core > + - const: cd [Severity: Medium] Since the top-level resets and reset-names maxItems were increased to 3, do the conditional branches for R-Car Gen2/3/4 and the subsequent fallback branch need to explicitly constrain resets and reset-names back to maxItems: 1? Without overriding the top-level relaxation here, it appears legacy controllers are now permitted to incorrectly define up to 3 resets. -- Sashiko AI review · https://sashiko.dev/#/patchset/20260622155610.184271-1-biju.das.jz@bp.renesas.com?part=1 ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-06-22 16:05 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-06-22 15:55 [PATCH v18 00/12] Add Renesas RZ/G3L SD/eMMC support Biju 2026-06-22 15:55 ` [PATCH v18 01/12] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC Biju 2026-06-22 16:05 ` sashiko-bot
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