* [PATCH v3 3/4] firmware: xilinx: Add support for Xilsem scan operations
2026-06-24 21:25 [PATCH v3 0/4] Add support for Versal Xilsem edac Rama devi Veggalam
2026-06-24 21:25 ` [PATCH v3 1/4] dt-bindings: edac: Add bindings for Xilinx Versal XilSEM Rama devi Veggalam
2026-06-24 21:25 ` [PATCH v3 2/4] Documentation: ABI: Add ABI doc for versal edac sysfs Rama devi Veggalam
@ 2026-06-24 21:25 ` Rama devi Veggalam
2026-06-24 21:39 ` sashiko-bot
2026-06-24 21:25 ` [PATCH v3 4/4] edac: xilinx: Add EDAC support for Versal XilSem Rama devi Veggalam
3 siblings, 1 reply; 11+ messages in thread
From: Rama devi Veggalam @ 2026-06-24 21:25 UTC (permalink / raw)
To: bp, tony.luck, michal.simek, robh, krzk+dt, conor+dt
Cc: linux-kernel, linux-edac, devicetree, james.morse, mchehab, rric,
git, Rama devi Veggalam
Add the ATF EEMI call support for Xilsem scan operations.
Initialize, start, stop scan, error inject, read configuration,
status and register for software error events.
Add macros for XilSem correctable and uncorrectable error events.
Signed-off-by: Rama devi Veggalam <rama.devi.veggalam@amd.com>
---
Changes in v3:
- created separate file for Xilsem ATF EEMI calls.
Changes in v2:
- Patch created on top of dependent patch series
"enhance zynqmp_pm_get_family_info()"
- Removed non-relevant SOB names in error event header files
- Updated copyright information
- Merged Versal and Versal NET error event definitions to firmware
patch
---
drivers/firmware/xilinx/Makefile | 2 +-
drivers/firmware/xilinx/zynqmp-sem.c | 176 ++++++++++++++++++
drivers/soc/xilinx/xlnx_event_manager.c | 6 +-
.../linux/firmware/xlnx-versal-error-events.h | 43 +++++
include/linux/firmware/xlnx-zynqmp-sem.h | 69 +++++++
include/linux/firmware/xlnx-zynqmp.h | 1 +
6 files changed, 294 insertions(+), 3 deletions(-)
create mode 100644 drivers/firmware/xilinx/zynqmp-sem.c
create mode 100644 include/linux/firmware/xlnx-versal-error-events.h
create mode 100644 include/linux/firmware/xlnx-zynqmp-sem.h
diff --git a/drivers/firmware/xilinx/Makefile b/drivers/firmware/xilinx/Makefile
index 8db0e66b6b7e..f9380c8931ae 100644
--- a/drivers/firmware/xilinx/Makefile
+++ b/drivers/firmware/xilinx/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
# Makefile for Xilinx firmwares
-obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o zynqmp-ufs.o zynqmp-crypto.o
+obj-$(CONFIG_ZYNQMP_FIRMWARE) += zynqmp.o zynqmp-sem.o zynqmp-ufs.o zynqmp-crypto.o
obj-$(CONFIG_ZYNQMP_FIRMWARE_DEBUG) += zynqmp-debug.o
diff --git a/drivers/firmware/xilinx/zynqmp-sem.c b/drivers/firmware/xilinx/zynqmp-sem.c
new file mode 100644
index 000000000000..5cd399b165f5
--- /dev/null
+++ b/drivers/firmware/xilinx/zynqmp-sem.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Firmware layer for XilSEM APIs.
+ *
+ * Copyright (C), 2026 Advanced Micro Devices, Inc.
+ */
+
+#include <linux/export.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+
+/**
+ * zynqmp_pm_xilsem_cntrl_ops - PM call to perform XilSEM operations
+ * @cmd: Command for XilSEM scan control operations
+ * @slrid: SLR id on which scan operation to be done
+ * @response: Output response (command header, error code or status, slr id)
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_cntrl_ops(u32 cmd, u32 slrid, u32 *const response)
+{
+ u32 ret_buf[PAYLOAD_ARG_CNT];
+ int ret;
+
+ ret = zynqmp_pm_invoke_fn(PM_XSEM_HEADER | cmd, ret_buf, 1, slrid);
+ response[0] = ret_buf[1];
+ response[1] = ret_buf[2];
+ response[2] = ret_buf[3];
+ response[3] = ret_buf[4];
+ response[4] = ret_buf[5];
+ response[5] = ret_buf[6];
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_cntrl_ops);
+
+/**
+ * zynqmp_pm_xilsem_cram_errinj - PM call to perform CRAM error injection
+ * @slrid: SLR id to inject error in CRAM
+ * @frame: Frame number to be used for error injection
+ * @qword: Word number to be used for error injection
+ * @bit: Bit location to be used for error injection
+ * @row: CFRAME row number to be used for error injection
+ * @response: Output response (command header, error code or status, slr id)
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_cram_errinj(u32 slrid, u32 frame, u32 qword, u32 bit, u32 row,
+ u32 *const response)
+{
+ u32 ret_buf[PAYLOAD_ARG_CNT];
+ int ret;
+
+ ret = zynqmp_pm_invoke_fn(PM_XSEM_CRAM_ERRINJ, ret_buf, 5, slrid, frame, qword, bit, row);
+ response[0] = ret_buf[1];
+ response[1] = ret_buf[2];
+ response[2] = ret_buf[3];
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_cram_errinj);
+
+/**
+ * zynqmp_pm_xilsem_cram_readecc - PM call to perform CFRAME ECC read
+ * @slrid: SLR id on which Frame ECC read to be done
+ * @frame: Frame number to be used for reading ECC
+ * @row: CFRAME row number to be used for reading ECC
+ * @response: Output response (Frame ecc header, ECC values, status)
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_cram_readecc(u32 slrid, u32 frame, u32 row, u32 *const response)
+{
+ u32 ret_buf[PAYLOAD_ARG_CNT];
+ int ret;
+
+ ret = zynqmp_pm_invoke_fn(PM_XSEM_CRAM_RD_ECC, ret_buf, 3, slrid, frame, row);
+ response[0] = ret_buf[1];
+ response[1] = ret_buf[2];
+ response[2] = ret_buf[3];
+ response[3] = ret_buf[4];
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_cram_readecc);
+
+/**
+ * zynqmp_pm_xilsem_read_cfg - PM call to perform Xilsem configuration read
+ * @slrid: SLR id for which configuration to be read
+ * @response: Output response (config header, Xilsem config, status)
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_read_cfg(u32 slrid, u32 *const response)
+{
+ u32 ret_buf[PAYLOAD_ARG_CNT];
+ int ret;
+
+ ret = zynqmp_pm_invoke_fn(PM_XSEM_RD_CONFIG, ret_buf, 1, slrid);
+ response[0] = ret_buf[1];
+ response[1] = ret_buf[2];
+ response[2] = ret_buf[3];
+ response[3] = ret_buf[4];
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_read_cfg);
+
+/**
+ * zynqmp_pm_xilsem_read_ssit_status - PM call to perform Xilsem SSIT status
+ * @slrid: SLR id for which ECC read to be done
+ * @bufaddr: Buffer address to get the status information
+ * @response: Output response (status read header, slr id)
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_read_ssit_status(u32 slrid, u32 bufaddr, u32 *const response)
+{
+ u32 ret_buf[PAYLOAD_ARG_CNT];
+ int ret;
+
+ ret = zynqmp_pm_invoke_fn(PM_XSEM_SSIT_RD_STS, ret_buf, 2, slrid, bufaddr);
+ response[0] = ret_buf[1];
+ response[1] = ret_buf[2];
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_read_ssit_status);
+
+/**
+ * zynqmp_pm_xilsem_cram_getcrc - PM call to perform CRAM Row CRC read
+ * @slrid: SLR id for which CRC read to be done
+ * @rowindex: CFRAME row number to be used for reading CRC
+ * @response: Output response (Get CRC header, CRC values, status)
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_cram_getcrc(u32 slrid, u32 rowindex, u32 *const response)
+{
+ u32 ret_buf[PAYLOAD_ARG_CNT];
+ int ret;
+
+ ret = zynqmp_pm_invoke_fn(PM_XSEM_SSIT_GET_CRC, ret_buf, 2, slrid, rowindex);
+ response[0] = ret_buf[1];
+ response[1] = ret_buf[2];
+ response[2] = ret_buf[3];
+ response[3] = ret_buf[4];
+ response[4] = ret_buf[5];
+ response[5] = ret_buf[6];
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_cram_getcrc);
+
+/**
+ * zynqmp_pm_xilsem_cram_ssit_totframes - PM call to perform total frames read
+ * @slrid: SLR id for which total frames read to be done
+ * @row: CFRAME row number to be used for reading ECC
+ * @framecnt: Buffer address to get toral frames data
+ * @response: Output response (Total frames header, slr id, row, status)
+ *
+ * Return: Returns 0 on success or error value on failure.
+ */
+int zynqmp_pm_xilsem_cram_ssit_totframes(u32 slrid, u32 row, u32 framecnt, u32 *const response)
+{
+ u32 ret_buf[PAYLOAD_ARG_CNT];
+ int ret;
+
+ ret = zynqmp_pm_invoke_fn(PM_XSEM_SSIT_GET_FRAMES, ret_buf, 3, slrid, row, framecnt);
+ response[0] = ret_buf[1];
+ response[1] = ret_buf[2];
+ response[2] = ret_buf[3];
+ response[3] = ret_buf[4];
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_xilsem_cram_ssit_totframes);
diff --git a/drivers/soc/xilinx/xlnx_event_manager.c b/drivers/soc/xilinx/xlnx_event_manager.c
index f733dc42b3b1..fb820fb15173 100644
--- a/drivers/soc/xilinx/xlnx_event_manager.c
+++ b/drivers/soc/xilinx/xlnx_event_manager.c
@@ -3,12 +3,13 @@
* Xilinx Event Management Driver
*
* Copyright (C) 2021 Xilinx, Inc.
- * Copyright (C) 2024 Advanced Micro Devices, Inc.
+ * Copyright (C) 2024-2026 Advanced Micro Devices, Inc.
*
* Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
*/
#include <linux/cpuhotplug.h>
+#include <linux/firmware/xlnx-versal-error-events.h>
#include <linux/firmware/xlnx-event-manager.h>
#include <linux/firmware/xlnx-zynqmp.h>
#include <linux/hashtable.h>
@@ -85,7 +86,8 @@ static bool xlnx_is_error_event(const u32 node_id)
if (node_id == VERSAL_EVENT_ERROR_PMC_ERR1 ||
node_id == VERSAL_EVENT_ERROR_PMC_ERR2 ||
node_id == VERSAL_EVENT_ERROR_PSM_ERR1 ||
- node_id == VERSAL_EVENT_ERROR_PSM_ERR2)
+ node_id == VERSAL_EVENT_ERROR_PSM_ERR2 ||
+ node_id == VERSAL_EVENT_ERROR_SW_ERR)
return true;
} else if (pm_family_code == PM_VERSAL_NET_FAMILY_CODE) {
if (node_id == VERSAL_NET_EVENT_ERROR_PMC_ERR1 ||
diff --git a/include/linux/firmware/xlnx-versal-error-events.h b/include/linux/firmware/xlnx-versal-error-events.h
new file mode 100644
index 000000000000..4767a23c9e4d
--- /dev/null
+++ b/include/linux/firmware/xlnx-versal-error-events.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx Versal Error Event Node IDs and Error Event Mask.
+ * Use with Xilinx Event Management Driver
+ *
+ * Copyright (C) 2021-2022 Xilinx
+ * Copyright (C) 2023-2026 Advanced Micro Devices, Inc.
+ *
+ */
+
+#ifndef _FIRMWARE_XLNX_VERSAL_ERROR_EVENTS_H_
+#define _FIRMWARE_XLNX_VERSAL_ERROR_EVENTS_H_
+
+/*
+ * Error Event Node Ids
+ */
+#define VERSAL_EVENT_ERROR_PMC_ERR1 (0x28100000U)
+#define VERSAL_EVENT_ERROR_PMC_ERR2 (0x28104000U)
+#define VERSAL_EVENT_ERROR_PSM_ERR1 (0x28108000U)
+#define VERSAL_EVENT_ERROR_PSM_ERR2 (0x2810C000U)
+#define VERSAL_EVENT_ERROR_SW_ERR (0x28110000U)
+
+/*
+ * XPM_VERSAL_EVENT_ERROR_MASK_XSEM_CRAM_CE_5: Error event mask for handling
+ * correctable error in Versal Configuration RAM which is reported by
+ * Soft Error Mitigation (XilSEM).
+ */
+#define XPM_VERSAL_EVENT_ERROR_MASK_XSEM_CRAM_CE_5 BIT(5)
+
+/**
+ * XPM_VERSAL_EVENT_ERROR_MASK_XSEM_CRAM_UE_6: Error event mask for handling
+ * uncorrectable error in Versal Configuration RAM which is reported by
+ * Soft Error Mitigation (XilSEM).
+ */
+#define XPM_VERSAL_EVENT_ERROR_MASK_XSEM_CRAM_UE_6 BIT(6)
+
+/**
+ * XPM_VERSAL_EVENT_ERROR_MASK_XSEM_NPI_UE_7: Error event mask for handling
+ * uncorrectable error in Versal NoC programming interface (NPI)
+ * register which is reported by Soft Error Mitigation (XilSEM).
+ */
+#define XPM_VERSAL_EVENT_ERROR_MASK_XSEM_NPI_UE_7 BIT(7)
+#endif /* _FIRMWARE_XLNX_VERSAL_ERROR_EVENTS_H_ */
diff --git a/include/linux/firmware/xlnx-zynqmp-sem.h b/include/linux/firmware/xlnx-zynqmp-sem.h
new file mode 100644
index 000000000000..722849cc6403
--- /dev/null
+++ b/include/linux/firmware/xlnx-zynqmp-sem.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Firmware layer for XilSEM APIs.
+ *
+ * Copyright (C), 2026 Advanced Micro Devices, Inc.
+ */
+
+#ifndef __FIRMWARE_ZYNQMP_SEM_H__
+#define __FIRMWARE_ZYNQMP_SEM_H__
+
+/* XilSEM commands */
+#define PM_XSEM_HEADER 0x300
+#define PM_XSEM_CRAM_ERRINJ 0x304
+#define PM_XSEM_RD_CONFIG 0x309
+#define PM_XSEM_CRAM_RD_ECC 0x30B
+#define PM_XSEM_SSIT_GET_CRC 0x30C
+#define PM_XSEM_SSIT_RD_STS 0x30D
+#define PM_XSEM_SSIT_GET_FRAMES 0x30E
+
+#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
+int zynqmp_pm_xilsem_cntrl_ops(u32 cmd, u32 slrid, u32 *const response);
+int zynqmp_pm_xilsem_cram_errinj(u32 slrid, u32 frame, u32 qword, u32 bit, u32 row,
+ u32 *const response);
+int zynqmp_pm_xilsem_cram_readecc(u32 slrid, u32 frame, u32 row, u32 *const response);
+int zynqmp_pm_xilsem_read_cfg(u32 slrid, u32 *const response);
+int zynqmp_pm_xilsem_read_ssit_status(u32 slrid, u32 bufaddr, u32 *const response);
+int zynqmp_pm_xilsem_cram_getcrc(u32 slrid, u32 rowindex, u32 *const response);
+int zynqmp_pm_xilsem_cram_ssit_totframes(u32 slrid, u32 row, u32 framecnt,
+ u32 *const response);
+#else
+static inline int zynqmp_pm_xilsem_cntrl_ops(u32 cmd, u32 slrid, u32 *const response)
+{
+ return -ENODEV;
+}
+
+static inline int zynqmp_pm_xilsem_cram_errinj(u32 slrid, u32 frame, u32 qword, u32 bit, u32 row,
+ u32 *const response)
+{
+ return -ENODEV;
+}
+
+static inline int zynqmp_pm_xilsem_cram_readecc(u32 slrid, u32 frame, u32 row, u32 *const response)
+{
+ return -ENODEV;
+}
+
+static inline int zynqmp_pm_xilsem_read_cfg(u32 slrid, u32 *const response)
+{
+ return -ENODEV;
+}
+
+static inline int zynqmp_pm_xilsem_read_ssit_status(u32 slrid, u32 bufaddr, u32 *const response)
+{
+ return -ENODEV;
+}
+
+static inline int zynqmp_pm_xilsem_cram_getcrc(u32 slrid, u32 rowindex, u32 *const response)
+{
+ return -ENODEV;
+}
+
+static inline int zynqmp_pm_xilsem_cram_ssit_totframes(u32 slrid, u32 row, u32 framecnt,
+ u32 *const response)
+{
+ return -ENODEV;
+}
+#endif
+
+#endif /* __FIRMWARE_ZYNQMP_SEM_H__ */
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 7e27b0f7bf7e..f5808f39c7a6 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -18,6 +18,7 @@
#include <linux/err.h>
#include <linux/firmware/xlnx-zynqmp-ufs.h>
#include <linux/firmware/xlnx-zynqmp-crypto.h>
+#include <linux/firmware/xlnx-zynqmp-sem.h>
#define ZYNQMP_PM_VERSION_MAJOR 1
#define ZYNQMP_PM_VERSION_MINOR 0
--
2.23.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 4/4] edac: xilinx: Add EDAC support for Versal XilSem
2026-06-24 21:25 [PATCH v3 0/4] Add support for Versal Xilsem edac Rama devi Veggalam
` (2 preceding siblings ...)
2026-06-24 21:25 ` [PATCH v3 3/4] firmware: xilinx: Add support for Xilsem scan operations Rama devi Veggalam
@ 2026-06-24 21:25 ` Rama devi Veggalam
2026-06-24 21:37 ` sashiko-bot
3 siblings, 1 reply; 11+ messages in thread
From: Rama devi Veggalam @ 2026-06-24 21:25 UTC (permalink / raw)
To: bp, tony.luck, michal.simek, robh, krzk+dt, conor+dt
Cc: linux-kernel, linux-edac, devicetree, james.morse, mchehab, rric,
git, Rama devi Veggalam
Xilinx Versal Soft Error Mitigation (XilSEM) is responsible for reporting
and optionally correcting soft errors in Configuration Memory of Versal.
The Configuration Memory includes Configuration RAM and
Network on Chip (NoC) peripheral interconnect (NPI) Registers.
The Configuration RAM (CRAM) memory is used for storing configuration
data for the programmable logic (PL) fabric. The NPI registers are used
for configuring the memory controllers, miscellaneous integrated hardware,
NoC interface units in the Veral device.
Add support to handle correctable and uncorrectable error events
from XilSEM.
Add sysfs interface for XilSEM scan operations
initialize, start, stop scan, error inject, read ECC, scan status and
configuration values.
Signed-off-by: Rama devi Veggalam <rama.devi.veggalam@amd.com>
---
Changes in v3:
- Merged Versal XilSem edac with Versal edac
Changes in v2:
- Patch created on top of dependent patch series
"enhance zynqmp_pm_get_family_info()"
- Fixed maximum length warning in patch description
- Added details for eprobe_defer conditions
- Updated copyright information
- Removed ARCH_ZYNQMP in dependent list of XilSEM Kconfig
- Added error code for invalid versal device type
- Removed redundant sysfs details in function headers
- Included MAINTAINERS to this patch
- Added more description in commit message
- Removed print for probe success
- Removed function comments for xsem_edac_remove()
---
MAINTAINERS | 1 +
drivers/edac/Kconfig | 4 +-
drivers/edac/versal_edac.c | 1348 +++++++++++++++++++++++++++++++++++-
3 files changed, 1349 insertions(+), 4 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9b787bc2855f..3109d05c324a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -29585,6 +29585,7 @@ F: include/uapi/linux/xilinx-v4l2-controls.h
XILINX VERSAL EDAC DRIVER
M: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
M: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
+M: Rama Devi Veggalam <rama.devi.veggalam@amd.com>
S: Maintained
F: Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
F: drivers/edac/versal_edac.c
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index a44b85c440ca..1549dbff3666 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -546,11 +546,11 @@ config EDAC_NPCM
device used to store data is used for ECC storage).
config EDAC_VERSAL
- tristate "Xilinx Versal DDR Memory Controller"
+ tristate "Xilinx Versal DDR Memory Controller and XilSEM"
depends on ARCH_ZYNQMP || COMPILE_TEST
help
Support for error detection and correction on the Xilinx Versal DDR
- memory controller.
+ memory controller and configuration memory of the programmable logic (PL) fabric. Support detection of errors in Network on Chip (NoC) peripheral interconnect (NPI) Registers.
Report both single bit errors (CE) and double bit errors (UE).
Support injecting both correctable and uncorrectable errors
diff --git a/drivers/edac/versal_edac.c b/drivers/edac/versal_edac.c
index 5a43b5d43ca2..024ddd90f699 100644
--- a/drivers/edac/versal_edac.c
+++ b/drivers/edac/versal_edac.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Versal memory controller driver
- * Copyright (C) 2023 Advanced Micro Devices, Inc.
+ * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc.
*/
#include <linux/bitfield.h>
#include <linux/edac.h>
@@ -11,12 +11,88 @@
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
#include <linux/sizes.h>
+#include <linux/io.h>
#include <linux/firmware/xlnx-zynqmp.h>
+#include <linux/firmware/xlnx-versal-error-events.h>
#include <linux/firmware/xlnx-event-manager.h>
#include "edac_module.h"
+/* XilSem CE Error log count */
+#define XILSEM_MAX_CE_LOG_CNT 7
+
+/** Maximum CRAM error register count */
+#define MAX_CRAMERR_REG_CNT 14
+/** Maximum NPI slave skip count */
+#define MAX_NPI_SLV_SKIP_CNT 8
+/** Maximum NPI Error info count */
+#define MAX_NPI_ERR_INFO_CNT 2
+
+/* Maximum SLR count */
+#define MAX_SLR_ID 3
+
+/** Maximum number of cframe types */
+#define CFRAME_MAX_TYPE 7
+
+/** Mask for getting Type_0, Type_4 frames */
+#define CFRAME_TYPE_0_4_MASK GENMASK(19, 0)
+
+/** Low mask, High mask for getting Type_1, Type_5 frames */
+#define CFRAME_TYPE_1_5_MASK_L GENMASK(39, 20)
+#define CFRAME_TYPE_1_5_MASK_H GENMASK(7, 0)
+
+/** Shift for getting Type_1, Type_5 frames */
+#define CFRAME_TYPE_1_5_SHIFT_R 0x20
+#define CFRAME_TYPE_1_5_SHIFT_L 0x12
+
+/** Mask for getting Type_2, Type_6 frames */
+#define CFRAME_TYPE_2_6_MASK GENMASK(27, 8)
+
+/** Shift for getting Type_2, Type_6 frames */
+#define CFRAME_TYPE_2_6_SHIFT_R 0x8
+
+/** Low mask, high mask for getting Type_3 frames */
+#define CFRAME_TYPE_3_MASK_L GENMASK(31, 28)
+#define CFRAME_TYPE_3_MASK_H GENMASK(15, 0)
+
+/** Shift for getting Type_3 */
+#define CFRAME_TYPE_3_SHIFT_R 0x28
+#define CFRAME_TYPE_3_SHIFT_L 0x4
+
+/* XilSem_CRAM scan error info registers */
+#define CRAM_STS_INFO_OFFSET 0x34
+#define CRAM_CE_ADDRL0_OFFSET 0x38
+#define CRAM_CE_ADDRH0_OFFSET 0x3C
+#define CRAM_CE_COUNT_OFFSET 0x70
+
+/* XilSem_NPI_Scan uncorrectable error info registers */
+#define NPI_SCAN_COUNT 0x24
+#define NPI_SCAN_HB_COUNT 0x28
+#define NPI_ERR0_INFO_OFFSET 0x2C
+#define NPI_ERR1_INFO_OFFSET 0x30
+
+/* XilSem bit masks for extracting error details */
+#define CRAM_ERR_ROW_MASK GENMASK(26, 23)
+#define CRAM_ERR_BIT_MASK GENMASK(22, 16)
+#define CRAM_ERR_QWRD_MASK GENMASK(27, 23)
+#define CRAM_ERR_FRAME_MASK GENMASK(22, 0)
+
+enum xsem_cmd_id {
+ CRAM_INIT_SCAN = 1, /* To initialize CRAM scan */
+ CRAM_START_SCAN = 2, /* To start CRAM scan */
+ CRAM_STOP_SCAN = 3, /* To stop CRAM scan */
+ CRAM_ERR_INJECT = 4, /* To inject CRAM error */
+ NPI_START_SCAN = 5, /* To start NPI scan */
+ NPI_STOP_SCAN = 6, /* To stop NPI scan */
+ NPI_ERR_INJECT = 7, /* To inject NPI error */
+};
+
+/* XilSem Module IDs */
+#define CRAM_MOD_ID 0x1
+#define NPI_MOD_ID 0x2
+
/* Granularity of reported error in bytes */
#define XDDR_EDAC_ERR_GRAIN 1
@@ -205,6 +281,105 @@ struct ecc_status {
u8 error_type;
};
+/* XILSEM structures */
+/**
+ * struct xsem_ecc_error_info - ECC error log information
+ * @status: CRAM/NPI scan error status
+ * @data0: Checksum of the error descriptor
+ * @data1: Index of the error descriptor
+ * @frame_addr: Frame location at which error occurred
+ * @block_type: Block type
+ * @row_id: Row number
+ * @bit_loc: Bit position in the Qword
+ * @qword: Qword location in the frame
+ */
+struct xsem_ecc_error_info {
+ u32 status;
+ u32 data0;
+ u32 data1;
+ u32 frame_addr;
+ u8 block_type;
+ u8 row_id;
+ u8 bit_loc;
+ u8 qword;
+};
+
+/**
+ * struct xsem_error_status - ECC status information to report
+ * @ce_cnt: Correctable error count
+ * @ue_cnt: Uncorrectable error count
+ * @ceinfo: Correctable error log information
+ * @ueinfo: Uncorrectable error log information
+ */
+struct xsem_error_status {
+ u32 ce_cnt;
+ u32 ue_cnt;
+ struct xsem_ecc_error_info ceinfo;
+ struct xsem_ecc_error_info ueinfo;
+};
+
+/**
+ * struct xsem_ssit_status - SSIT status information
+ * @npi_status: NPI Status
+ * @slvskpcnt: NPI Slave skip count
+ * @scancnt: NPI Scan count
+ * @hbcnt: NPI Heartbeat count
+ * @err_info: NPI Error Information
+ * @cram_status: Cram Status
+ * @err_addr: Address of corrected error location
+ * @errcnt: Corrected Error count.
+ */
+struct xsem_ssit_status {
+ u32 npi_status;
+ u32 slvskpcnt[MAX_NPI_SLV_SKIP_CNT];
+ u32 scancnt;
+ u32 hbcnt;
+ u32 err_info[MAX_NPI_ERR_INFO_CNT];
+ u32 cram_status;
+ u32 err_addr[MAX_CRAMERR_REG_CNT];
+ u32 errcnt;
+};
+
+/**
+ * struct xsem_rtca_priv - Xilsem private instance data
+ * @baseaddr: Base address of the XilSem PLM RTCA module
+ * @cram_get_frames_status: Buffer for get total frames command
+ * @cram_get_crc_status: Buffer for CRC read command
+ * @xilsem_ssit_status: Buffer for SLR status command
+ * @cram_errinj_status: Buffer for CRAM error injection
+ * @cram_total_frames: Buffer for total cframes data
+ * @scan_ctrl_status: Buffer for scan ctrl commands
+ * @cram_frame_ecc: Buffer for CRAM frame ECC
+ * @xilsem_status: Buffer for CRAM & NPI status
+ * @xilsem_cfg: Buffer for CRAM & NPI configuration
+ * @sw_event_node_id: Error event node Id
+ * @cram_ce_mask: Event bit mask for CRAM correctable error
+ * @cram_ue_mask: Event bit mask for CRAM uncorrectable error
+ * @npi_ue_mask: Event bit mask for NPI uncorrectable error
+ * @cram_ce_cnt: Correctable Error count
+ * @cram_ue_cnt: Uncorrectable Error count
+ * @slr_info: Pointer to get SSIT status information
+ */
+struct xsem_rtca_priv {
+ void __iomem *baseaddr;
+ u32 cram_get_frames_status[4];
+ u32 cram_get_crc_status[6];
+ u32 xilsem_ssit_status[4];
+ u32 cram_errinj_status[3];
+ u32 cram_total_frames[7];
+ u32 scan_ctrl_status[7];
+ u32 cram_frame_ecc[4];
+ u32 xilsem_status[4];
+ u32 xilsem_cfg[6];
+ u32 sw_event_node_id;
+ u32 cram_ce_mask;
+ u32 cram_ue_mask;
+ u32 npi_ue_mask;
+ u32 cram_ce_cnt;
+ u32 cram_ue_cnt;
+ struct xsem_ssit_status *slr_info;
+};
+
/**
* struct edac_priv - DDR memory controller private instance data.
* @ddrmc_baseaddr: Base address of the DDR controller.
@@ -227,6 +402,8 @@ struct ecc_status {
struct edac_priv {
void __iomem *ddrmc_baseaddr;
void __iomem *ddrmc_noc_baseaddr;
+ void __iomem *sem_baseaddr;
+ struct xsem_rtca_priv *xsem_rtca;
char message[XDDR_EDAC_MSG_SIZE];
u32 mc_id;
u32 ce_cnt;
@@ -1073,14 +1250,1108 @@ static u32 emif_get_id(struct device_node *node)
return my_id;
}
+/**
+ * xsem_scan_control_show - Shows scan control operation status
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ *
+ * Shows the scan control operations status
+ * Return: Number of bytes copied.
+ */
+static ssize_t xsem_scan_control_show(struct device *dev,
+ struct device_attribute *mattr,
+ char *data)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ return sprintf(data, "[0x%x][0x%x][0x%x][0x%x][0x%x][0x%x][0x%x]\n\r",
+ priv->xsem_rtca->scan_ctrl_status[0],
+ priv->xsem_rtca->scan_ctrl_status[0],
+ priv->xsem_rtca->scan_ctrl_status[1],
+ priv->xsem_rtca->scan_ctrl_status[2],
+ priv->xsem_rtca->scan_ctrl_status[3],
+ priv->xsem_rtca->scan_ctrl_status[4],
+ priv->xsem_rtca->scan_ctrl_status[5]);
+}
+
+/**
+ * xsem_scan_control_store - Set scan control operation
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ * @count: read the size bytes from buffer
+ *
+ * User-space interface for doing Xilsem scan operations
+ * (initialization, start, stop)
+ * Return: count argument if request succeeds, else error code
+ */
+static ssize_t xsem_scan_control_store(struct device *dev,
+ struct device_attribute *mattr,
+ const char *data, size_t count)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ char *kern_buff, *inbuf, *tok;
+ u32 cmd;
+ u32 slrid;
+ int ret;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ kern_buff = kzalloc(count, GFP_KERNEL);
+ if (!kern_buff)
+ return -ENOMEM;
+ strscpy(kern_buff, data, count);
+
+ inbuf = kern_buff;
+
+ if (!data) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ /* Read Scan command */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &cmd);
+ if (ret) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Read SLR number */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &slrid);
+ if (ret) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ if (cmd < CRAM_INIT_SCAN || cmd > NPI_ERR_INJECT || cmd == CRAM_ERR_INJECT) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ if (slrid > MAX_SLR_ID) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = zynqmp_pm_xilsem_cntrl_ops(cmd, slrid, priv->xsem_rtca->scan_ctrl_status);
+err:
+ kfree(kern_buff);
+
+ if (ret)
+ return ret;
+
+ return count;
+}
+
+/**
+ * xsem_cram_injecterr_show - Shows CRAM error injection status
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ *
+ * Shows CRAM error injection status
+ * Return: Number of bytes copied.
+ */
+static ssize_t xsem_cram_injecterr_show(struct device *dev,
+ struct device_attribute *mattr,
+ char *data)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ return sprintf(data, "[0x%x][0x%x][0x%x]]\n\r",
+ priv->xsem_rtca->cram_errinj_status[0],
+ priv->xsem_rtca->cram_errinj_status[1],
+ priv->xsem_rtca->cram_errinj_status[2]);
+}
+
+/**
+ * xsem_cram_injecterr_store - Start error injection
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ * @count: read the size bytes from buffer
+ *
+ * User-space interface for doing CRAM error injection
+ * Return: count argument if request succeeds, else error code
+ */
+static ssize_t xsem_cram_injecterr_store(struct device *dev,
+ struct device_attribute *mattr,
+ const char *data, size_t count)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ char *kern_buff, *inbuf, *tok;
+ u32 row, frame, qword, bitloc, slrid;
+ int ret;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ kern_buff = kzalloc(count, GFP_KERNEL);
+ if (!kern_buff)
+ return -ENOMEM;
+
+ strscpy(kern_buff, data, count);
+
+ inbuf = kern_buff;
+
+ /* Read Frame number */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &frame);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ /* Read Qword number */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &qword);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ /* Read Bit location */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &bitloc);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ /* Read Row number */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &row);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ /* Read slr id */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &slrid);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ if (slrid > MAX_SLR_ID) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = zynqmp_pm_xilsem_cram_errinj(slrid, frame, qword, bitloc, row,
+ priv->xsem_rtca->cram_errinj_status);
+err:
+ kfree(kern_buff);
+
+ if (ret)
+ return ret;
+
+ return count;
+}
+
+/**
+ * xsem_cram_framecc_read_show - Shows CRAM Frame ECC
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ *
+ * Shows CRAM Frame ECC value
+ * Return: Number of bytes copied.
+ */
+static ssize_t xsem_cram_framecc_read_show(struct device *dev,
+ struct device_attribute *mattr,
+ char *data)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ int offset = 0;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ offset += sprintf(data + offset, "Read Frame ECC Cmd: [0x%x]\n\r",
+ priv->xsem_rtca->cram_frame_ecc[0]);
+ offset += sprintf(data + offset, "Frame ECC Word_0: [0x%x]\n\r",
+ priv->xsem_rtca->cram_frame_ecc[1]);
+ offset += sprintf(data + offset, "Frame ECC Word_1: [0x%x]\n\r",
+ priv->xsem_rtca->cram_frame_ecc[2]);
+ offset += sprintf(data + offset, "Cmd Status: [0x%x]\n\r",
+ priv->xsem_rtca->cram_frame_ecc[3]);
+
+ return offset;
+}
+
+/**
+ * xsem_cram_framecc_read_store - Read CRAM Frame ECC
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ * @count: read the size bytes from buffer
+ *
+ * User-space interface for reading CRAM frame ECC
+ * Return: count argument if request succeeds, else error code
+ */
+static ssize_t xsem_cram_framecc_read_store(struct device *dev,
+ struct device_attribute *mattr,
+ const char *data, size_t count)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ char *kern_buff, *inbuf, *tok;
+ u32 frameaddr, row, slrid;
+ int ret;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ kern_buff = kzalloc(count, GFP_KERNEL);
+ if (!kern_buff)
+ return -ENOMEM;
+
+ strscpy(kern_buff, data, count);
+
+ inbuf = kern_buff;
+
+ /* Read Frame address */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &frameaddr);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ /* Read Row number */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &row);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ /* Read slr id */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &slrid);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ if (slrid > MAX_SLR_ID) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = zynqmp_pm_xilsem_cram_readecc(slrid, frameaddr, row,
+ priv->xsem_rtca->cram_frame_ecc);
+err:
+ kfree(kern_buff);
+
+ if (ret)
+ return ret;
+
+ return count;
+}
+
+/**
+ * xsem_cram_ssit_getcrc_show - Shows CRAM Row CRC
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ *
+ * Shows CRAM Row CRC value
+ * Return: Number of bytes copied.
+ */
+static ssize_t xsem_cram_ssit_getcrc_show(struct device *dev,
+ struct device_attribute *mattr,
+ char *data)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ int offset = 0;
+ u32 id;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ offset += sprintf(data + offset, "Read CRC Cmd:[0x%x]\n\r",
+ priv->xsem_rtca->cram_get_crc_status[0]);
+ for (id = 0; id < 4; id++)
+ offset += sprintf(data + offset, "CRC_Word %d:[0x%x]\n\r", id,
+ priv->xsem_rtca->cram_get_crc_status[id + 1]);
+ offset += sprintf(data + offset, "Cmd status: [0x%x]\n\r",
+ priv->xsem_rtca->cram_get_crc_status[5]);
+
+ return offset;
+}
+
+/**
+ * xsem_cram_ssit_getcrc_store - Read CRAM row CRC
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ * @count: read the size bytes from buffer
+ *
+ * User-space interface for reading CRAM row CRC
+ * Return: count argument if request succeeds, else error code
+ */
+static ssize_t xsem_cram_ssit_getcrc_store(struct device *dev,
+ struct device_attribute *mattr,
+ const char *data, size_t count)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ char *kern_buff, *inbuf, *tok;
+ u32 rowindex, slrid;
+ int ret;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ kern_buff = kzalloc(count, GFP_KERNEL);
+ if (!kern_buff)
+ return -ENOMEM;
+
+ strscpy(kern_buff, data, count);
+
+ inbuf = kern_buff;
+
+ /* Read Row number */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &rowindex);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ /* Read SLR Id */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &slrid);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ if (slrid > MAX_SLR_ID) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = zynqmp_pm_xilsem_cram_getcrc(slrid, rowindex,
+ priv->xsem_rtca->cram_get_crc_status);
+err:
+ kfree(kern_buff);
+
+ if (ret)
+ return ret;
+
+ return count;
+}
+
+/**
+ * xsem_total_cframes_ssit_show - Shows total cframes
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ *
+ * Shows CRAM total cframes
+ * Return: Number of bytes copied.
+ */
+static ssize_t xsem_total_cframes_ssit_show(struct device *dev,
+ struct device_attribute *mattr,
+ char *data)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ u32 temp_buf[CFRAME_MAX_TYPE] = {0};
+ u32 id;
+ int offset = 0;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ for (id = 0; id < CFRAME_MAX_TYPE; id++)
+ temp_buf[id] = priv->xsem_rtca->cram_total_frames[id];
+
+ priv->xsem_rtca->cram_total_frames[0] = (temp_buf[0] & CFRAME_TYPE_0_4_MASK);
+ priv->xsem_rtca->cram_total_frames[1] = (temp_buf[0] &
+ CFRAME_TYPE_1_5_MASK_L) >> CFRAME_TYPE_1_5_SHIFT_R;
+ priv->xsem_rtca->cram_total_frames[1] |= (temp_buf[1] &
+ CFRAME_TYPE_1_5_MASK_H) << CFRAME_TYPE_1_5_SHIFT_L;
+ priv->xsem_rtca->cram_total_frames[2] = (temp_buf[1] &
+ CFRAME_TYPE_2_6_MASK) >> CFRAME_TYPE_2_6_SHIFT_R;
+ priv->xsem_rtca->cram_total_frames[3] = (temp_buf[1] &
+ CFRAME_TYPE_3_MASK_L) >> CFRAME_TYPE_3_SHIFT_R;
+ priv->xsem_rtca->cram_total_frames[3] |= (temp_buf[2] &
+ CFRAME_TYPE_3_MASK_H) << CFRAME_TYPE_3_SHIFT_L;
+ priv->xsem_rtca->cram_total_frames[4] = (temp_buf[4] & CFRAME_TYPE_0_4_MASK);
+ priv->xsem_rtca->cram_total_frames[5] = (temp_buf[4] &
+ CFRAME_TYPE_1_5_MASK_L) >> CFRAME_TYPE_1_5_SHIFT_R;
+ priv->xsem_rtca->cram_total_frames[5] |= (temp_buf[5] &
+ CFRAME_TYPE_1_5_MASK_H) << CFRAME_TYPE_1_5_SHIFT_L;
+ priv->xsem_rtca->cram_total_frames[6] = (temp_buf[5] &
+ CFRAME_TYPE_2_6_MASK) >> CFRAME_TYPE_2_6_SHIFT_R;
+
+ offset += sprintf(data + offset, "Read Total Frames Cmd : [0x%x]\n\r",
+ priv->xsem_rtca->cram_get_frames_status[0]);
+ offset += sprintf(data + offset, "SLR ID : [0x%x]\n\r",
+ priv->xsem_rtca->cram_get_frames_status[1]);
+ offset += sprintf(data + offset, "Row Index: [0x%x]\n\r",
+ priv->xsem_rtca->cram_get_frames_status[2]);
+ for (id = 0; id < CFRAME_MAX_TYPE; id++)
+ offset += sprintf(data + offset, "Type[%d] frame count: [%d]\n\r", id,
+ priv->xsem_rtca->cram_total_frames[id]);
+
+ offset += sprintf(data + offset, "Cmd Status: [0x%x]\n\r",
+ priv->xsem_rtca->cram_get_frames_status[3]);
+ return offset;
+}
+
+/**
+ * xsem_total_cframes_ssit_store - Read total cframes in CRAM
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ * @count: read the size bytes from buffer
+ *
+ * User-space interface for reading CRAM total frames in ssit device
+ * Return: count argument if request succeeds, else error code
+ */
+static ssize_t xsem_total_cframes_ssit_store(struct device *dev,
+ struct device_attribute *mattr,
+ const char *data, size_t count)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ char *kern_buff, *inbuf, *tok, *kbuf1;
+ dma_addr_t dma_addr = 0;
+ u32 row, slrid, dma_size;
+ int ret;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ kern_buff = kzalloc(count, GFP_KERNEL);
+ if (!kern_buff)
+ return -ENOMEM;
+
+ strscpy(kern_buff, data, count);
+
+ inbuf = kern_buff;
+
+ /* Read Row number */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &row);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ /* Read slr id */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &slrid);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ if (slrid > MAX_SLR_ID || row > 4) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ dma_size = sizeof(priv->xsem_rtca->cram_total_frames);
+ kbuf1 = dma_alloc_coherent(dev, dma_size, &dma_addr, GFP_KERNEL);
+ if (!kbuf1) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ret = zynqmp_pm_xilsem_cram_ssit_totframes(slrid, row, dma_addr,
+ priv->xsem_rtca->cram_get_frames_status);
+ if (ret) {
+ edac_printk(KERN_ERR, EDAC_MC, "ERROR: XilSEM Status PM API failed\n");
+ dma_free_coherent(dev, dma_size, kbuf1, dma_addr);
+ goto err;
+ }
+
+ memcpy(priv->xsem_rtca->cram_total_frames, kbuf1, dma_size);
+ dma_free_coherent(dev, dma_size, kbuf1, dma_addr);
+
+err:
+ kfree(kern_buff);
+
+ if (ret)
+ return ret;
+
+ return count;
+}
+
+/**
+ * xsem_read_status_show - Shows CRAM & NPI scan status
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ *
+ * Shows CRAM & NPI scan status
+ * Return: Number of bytes copied.
+ */
+static ssize_t xsem_read_status_show(struct device *dev,
+ struct device_attribute *mattr,
+ char *data)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ return sprintf(data, "[0x%x][0x%x][0x%x]\n\r",
+ priv->xsem_rtca->xilsem_status[0],
+ priv->xsem_rtca->xilsem_status[1],
+ priv->xsem_rtca->xilsem_status[2]);
+}
+
+/**
+ * xsem_read_status_store - Read CRAM & NPI scan status
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ * @count: read the size bytes from buffer
+ *
+ * User-space interface for reading Xilsem status
+ * Return: count argument if read succeeds, else error code
+ */
+static ssize_t xsem_read_status_store(struct device *dev,
+ struct device_attribute *mattr,
+ const char *data, size_t count)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ u32 module;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ if (!data)
+ return -EFAULT;
+
+ if (kstrtouint(data, 0, &module))
+ return -EINVAL;
+
+ if (module == CRAM_MOD_ID) {
+ if (priv->sem_baseaddr) {
+ priv->xsem_rtca->xilsem_status[0] = readl(priv->sem_baseaddr +
+ CRAM_STS_INFO_OFFSET);
+ priv->xsem_rtca->xilsem_status[1] = readl(priv->sem_baseaddr +
+ CRAM_CE_COUNT_OFFSET);
+ priv->xsem_rtca->xilsem_status[2] = 0;
+ }
+ } else if (module == NPI_MOD_ID) {
+ if (priv->sem_baseaddr) {
+ priv->xsem_rtca->xilsem_status[0] = readl(priv->sem_baseaddr);
+ priv->xsem_rtca->xilsem_status[1] = readl(priv->sem_baseaddr +
+ NPI_SCAN_COUNT);
+ priv->xsem_rtca->xilsem_status[2] = readl(priv->sem_baseaddr +
+ NPI_SCAN_HB_COUNT);
+ }
+ } else {
+ edac_printk(KERN_ERR, EDAC_MC, "Invalid module %d\n", module);
+ return -EINVAL;
+ }
+
+ return count;
+}
+
+/**
+ * xsem_read_ssit_status_show - Shows CRAM & NPI scan for SSIT device
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ *
+ * Shows CRAM & NPI scan status for given SLR
+ * Return: Number of bytes copied.
+ */
+static ssize_t xsem_read_ssit_status_show(struct device *dev,
+ struct device_attribute *mattr,
+ char *data)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ int offset = 0;
+ int id;
+
+ if (!priv->xsem_rtca || !priv->xsem_rtca->slr_info)
+ return -EINVAL;
+
+ offset += sprintf(data + offset, "Read SLR Status Cmd:[0x%x]\n\r",
+ priv->xsem_rtca->xilsem_ssit_status[0]);
+ offset += sprintf(data + offset, "SLR ID:[0x%x]\n\r",
+ priv->xsem_rtca->xilsem_ssit_status[1]);
+ offset += sprintf(data + offset, "NPI status:[0x%x]\n\r",
+ priv->xsem_rtca->slr_info->npi_status);
+ offset += sprintf(data + offset, "NPI scan count:[0x%x]\n\r",
+ priv->xsem_rtca->slr_info->scancnt);
+ offset += sprintf(data + offset, "NPI Heartbeat count:[0x%x]\n\r",
+ priv->xsem_rtca->slr_info->hbcnt);
+ for (id = 0; id < MAX_NPI_SLV_SKIP_CNT; id++)
+ offset += sprintf(data + offset, "NPI scan skip count %x :[0x%x]\n\r", id,
+ priv->xsem_rtca->slr_info->slvskpcnt[id]);
+
+ for (id = 0; id < MAX_NPI_ERR_INFO_CNT; id++)
+ offset += sprintf(data + offset, "NPI error info %x :[0x%x]\n\r", id,
+ priv->xsem_rtca->slr_info->err_info[id]);
+
+ offset += sprintf(data + offset, "CRAM status:[0x%x]\n\r",
+ priv->xsem_rtca->slr_info->cram_status);
+
+ for (id = 0U; id < 7; id++) {
+ offset += sprintf(data + offset, "Error Location High %x: [0x%x]\n\r", id,
+ priv->xsem_rtca->slr_info->err_addr[(id * 2) + 1]);
+ offset += sprintf(data + offset, "Error Location Low %x: [0x%x]\n\r", id,
+ priv->xsem_rtca->slr_info->err_addr[id * 2]);
+ }
+ offset += sprintf(data + offset, "CRAM scan CE count:[0x%x]\n\r",
+ priv->xsem_rtca->slr_info->errcnt);
+
+ return offset;
+}
+
+/**
+ * xsem_read_ssit_status_store - Read CRAM & NPI scan SSIT status
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ * @count: read the size bytes from buffer
+ *
+ * User-space interface for reading Xilsem status for SSIT device
+ * Return: count argument if read succeeds, else error code
+ */
+static ssize_t xsem_read_ssit_status_store(struct device *dev,
+ struct device_attribute *mattr,
+ const char *data, size_t count)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ char *kern_buff, *inbuf, *tok, *kbuf1;
+ size_t dma_size;
+ dma_addr_t dma_addr = 0;
+ u32 slrid;
+ int ret;
+
+ if (!priv->xsem_rtca || !priv->xsem_rtca->slr_info)
+ return -EINVAL;
+
+ kern_buff = kzalloc(count, GFP_KERNEL);
+ if (!kern_buff)
+ return -ENOMEM;
+
+ strscpy(kern_buff, data, count);
+
+ inbuf = kern_buff;
+
+ /* Read SLR ID */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &slrid);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ if (slrid > MAX_SLR_ID) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ dma_size = sizeof(struct xsem_ssit_status);
+
+ kbuf1 = dma_alloc_coherent(dev, dma_size, &dma_addr, GFP_KERNEL);
+ if (!kbuf1) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ret = zynqmp_pm_xilsem_read_ssit_status(slrid, dma_addr,
+ priv->xsem_rtca->xilsem_ssit_status);
+ if (ret) {
+ edac_printk(KERN_ERR, EDAC_MC, "ERROR: XilSEM Status PM API failed\n");
+ dma_free_coherent(dev, dma_size, kbuf1, dma_addr);
+ goto err;
+ }
+
+ memcpy(priv->xsem_rtca->slr_info, kbuf1, dma_size);
+
+ dma_free_coherent(dev, dma_size, kbuf1, dma_addr);
+err:
+ kfree(kern_buff);
+
+ if (ret)
+ return ret;
+
+ return count;
+}
+
+/**
+ * xsem_read_config_show - Shows CRAM & NPI configuration
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ *
+ * Shows CRAM & NPI configuration
+ * Return: Number of bytes copied.
+ */
+static ssize_t xsem_read_config_show(struct device *dev,
+ struct device_attribute *mattr,
+ char *data)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ int offset = 0;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ offset += sprintf(data + offset, "Read Config Cmd: [0x%x]\n\r",
+ priv->xsem_rtca->xilsem_cfg[0]);
+ offset += sprintf(data + offset, "CRAM Scan Config: [0x%x]\n\r",
+ priv->xsem_rtca->xilsem_cfg[1]);
+ offset += sprintf(data + offset, "NPI Scan Config: [0x%x]\n\r",
+ priv->xsem_rtca->xilsem_cfg[2]);
+ offset += sprintf(data + offset, "Cmd Status: [0x%x]\n\r",
+ priv->xsem_rtca->xilsem_cfg[3]);
+
+ return offset;
+}
+
+/**
+ * xsem_read_config_store - Read CRAM & NPI configuration
+ * @dev: Pointer to the device struct
+ * @mattr: Pointer to device attribute
+ * @data: Pointer to user data
+ * @count: read the size bytes from buffer
+ *
+ * User-space interface for reading Xilsem configuration
+ * Return: count argument if request succeeds, else error code
+ */
+static ssize_t xsem_read_config_store(struct device *dev,
+ struct device_attribute *mattr,
+ const char *data, size_t count)
+{
+ struct mem_ctl_info *mci = to_mci(dev);
+ struct edac_priv *priv = mci->pvt_info;
+ char *kern_buff, *inbuf, *tok;
+ u32 slrid;
+ int ret;
+
+ if (!priv->xsem_rtca)
+ return -EINVAL;
+
+ kern_buff = kzalloc(count, GFP_KERNEL);
+ if (!kern_buff)
+ return -ENOMEM;
+
+ strscpy(kern_buff, data, count);
+
+ inbuf = kern_buff;
+
+ /* Read SLR id */
+ tok = strsep(&inbuf, " ");
+ if (!tok) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ ret = kstrtouint(tok, 0, &slrid);
+ if (ret) {
+ ret = -EFAULT;
+ goto err;
+ }
+
+ if (slrid > MAX_SLR_ID) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = zynqmp_pm_xilsem_read_cfg(slrid, priv->xsem_rtca->xilsem_cfg);
+
+err:
+ kfree(kern_buff);
+
+ if (ret)
+ return ret;
+
+ return count;
+}
+
+/**
+ * xsem_geterror_info - Get the current ecc error info
+ * @mci: Pointer to the memory controller instance
+ * @p: Pointer to the Xilsem error status structure
+ * @mask: mask indicates the error type
+ *
+ * Determines there is any ecc error or not
+ */
+static void xsem_geterror_info(struct mem_ctl_info *mci, struct xsem_error_status *p,
+ int mask)
+{
+ struct edac_priv *priv = mci->pvt_info;
+ u32 error_word_0, error_word_1, ce_count;
+ u8 index;
+
+ if (!priv->xsem_rtca || !priv->sem_baseaddr)
+ return;
+
+ if (mask & priv->xsem_rtca->cram_ce_mask) {
+ p->ce_cnt++;
+
+ /* Read CRAM total correctable error count */
+ ce_count = readl(priv->sem_baseaddr + CRAM_CE_COUNT_OFFSET);
+ /* Calculate index for error log */
+ index = (ce_count % XILSEM_MAX_CE_LOG_CNT);
+ /*
+ * Check if addr index is not 0
+ * if yes, then decrement index, else set index as last entry
+ */
+ if (index != 0U) {
+ /* Decrement Index */
+ --index;
+ } else {
+ /* Set log index to 6 (Max-1) */
+ index = (XILSEM_MAX_CE_LOG_CNT - 1);
+ }
+ error_word_0 = readl(priv->sem_baseaddr + CRAM_CE_ADDRL0_OFFSET + (index * 8U));
+ error_word_1 = readl(priv->sem_baseaddr + CRAM_CE_ADDRH0_OFFSET + (index * 8U));
+
+ /* Frame is at 22:0 bits of SEM_CRAMERR_ADDRH0 reg */
+ p->ceinfo.frame_addr = FIELD_GET(CRAM_ERR_FRAME_MASK, error_word_1);
+
+ /* row is at 26:23 bits of SEM_CRAMERR_ADDRH0 reg */
+ p->ceinfo.row_id = FIELD_GET(CRAM_ERR_ROW_MASK, error_word_1);
+
+ /* bit is at 22:16 bits of SEM_CRAMERR_ADDRL0 reg */
+ p->ceinfo.bit_loc = FIELD_GET(CRAM_ERR_BIT_MASK, error_word_0);
+
+ /* Qword is at 27:23 bits of SEM_CRAMERR_ADDRL0 reg */
+ p->ceinfo.qword = FIELD_GET(CRAM_ERR_QWRD_MASK, error_word_0);
+
+ /* Read CRAM status */
+ p->ceinfo.status = readl(priv->sem_baseaddr + CRAM_STS_INFO_OFFSET);
+ } else if (mask & priv->xsem_rtca->cram_ue_mask) {
+ p->ue_cnt++;
+ p->ueinfo.data0 = 0;
+ p->ueinfo.data1 = 0;
+ p->ueinfo.status = readl(priv->sem_baseaddr + CRAM_STS_INFO_OFFSET);
+ } else if (mask & priv->xsem_rtca->npi_ue_mask) {
+ p->ue_cnt++;
+ p->ueinfo.data0 = readl(priv->sem_baseaddr + NPI_ERR0_INFO_OFFSET);
+ p->ueinfo.data1 = readl(priv->sem_baseaddr + NPI_ERR1_INFO_OFFSET);
+ p->ueinfo.status = readl(priv->sem_baseaddr);
+ } else {
+ edac_printk(KERN_ERR, EDAC_MC, "Invalid Event received %d\n", mask);
+ }
+}
+
+/**
+ * xsem_handle_error - Handle XilSem error types CE and UE
+ * @mci: Pointer to the memory controller instance
+ * @p: Pointer to the xilsem error status structure
+ *
+ * Handles the correctable and uncorrectable error.
+ */
+static void xsem_handle_error(struct mem_ctl_info *mci, struct xsem_error_status *p)
+{
+ struct xsem_ecc_error_info *pinf;
+ char message[XDDR_EDAC_MSG_SIZE];
+
+ if (p->ce_cnt) {
+ pinf = &p->ceinfo;
+ snprintf(message, XDDR_EDAC_MSG_SIZE,
+ "\n\rXILSEM CRAM error type :%s\n\r"
+ "\nFrame_Addr: [0x%X]\t Row_num: [0x%X]\t Bit_loc: [0x%X]\t Qword: [0x%X]\n\r",
+ "CE", pinf->frame_addr, pinf->row_id,
+ pinf->bit_loc, pinf->qword);
+
+ edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
+ p->ce_cnt, 0, 0, 0, 0, 0, -1,
+ message, "");
+ }
+
+ if (p->ue_cnt) {
+ pinf = &p->ueinfo;
+ snprintf(message, XDDR_EDAC_MSG_SIZE,
+ "\n\rXILSEM error type :%s\n\r"
+ "status: [0x%X]\n\rError_Info0: [0x%X]\n\r"
+ "Error_Info1: [0x%X]",
+ "UE", pinf->status, pinf->data0, pinf->data1);
+
+ edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
+ p->ue_cnt, 0, 0, 0, 0, 0, -1,
+ message, "");
+ }
+}
+
+/**
+ * xsem_err_callback - Handle Correctable and Uncorrectable errors.
+ * @payload: payload data.
+ * @data: controller data.
+ *
+ * Handles ECC correctable and uncorrectable errors.
+ */
+static void xsem_err_callback(const u32 *payload, void *data)
+{
+ struct xsem_error_status stat;
+ struct edac_priv *priv;
+ struct mem_ctl_info *mci = (struct mem_ctl_info *)data;
+ int event;
+
+ priv = mci->pvt_info;
+ if (!priv->xsem_rtca)
+ return;
+
+ memset(&stat, 0, sizeof(stat));
+ /* Read payload to get the event type */
+ event = payload[2];
+ edac_printk(KERN_INFO, EDAC_MC, "Event received %x\n", event);
+ xsem_geterror_info(mci, &stat, event);
+
+ priv->xsem_rtca->cram_ce_cnt += stat.ce_cnt;
+ priv->xsem_rtca->cram_ue_cnt += stat.ue_cnt;
+ xsem_handle_error(mci, &stat);
+}
+
+static DEVICE_ATTR_RW(xsem_scan_control);
+static DEVICE_ATTR_RW(xsem_cram_injecterr);
+static DEVICE_ATTR_RW(xsem_cram_framecc_read);
+static DEVICE_ATTR_RW(xsem_cram_ssit_getcrc);
+static DEVICE_ATTR_RW(xsem_read_status);
+static DEVICE_ATTR_RW(xsem_read_ssit_status);
+static DEVICE_ATTR_RW(xsem_total_cframes_ssit);
+static DEVICE_ATTR_RW(xsem_read_config);
+
+static struct attribute *xsem_edac_sysfs_attrs[] = {
+ &dev_attr_xsem_scan_control.attr,
+ &dev_attr_xsem_cram_injecterr.attr,
+ &dev_attr_xsem_cram_framecc_read.attr,
+ &dev_attr_xsem_cram_ssit_getcrc.attr,
+ &dev_attr_xsem_read_status.attr,
+ &dev_attr_xsem_read_ssit_status.attr,
+ &dev_attr_xsem_total_cframes_ssit.attr,
+ &dev_attr_xsem_read_config.attr,
+ NULL,
+};
+
+static const struct attribute_group xsem_edac_sysfs_attr_group = {
+ .attrs = xsem_edac_sysfs_attrs,
+};
+
+static int xsem_edac_create_sysfs_attributes(struct mem_ctl_info *mci)
+{
+ return sysfs_create_group(&mci->dev.kobj, &xsem_edac_sysfs_attr_group);
+}
+
+static void xsem_edac_remove_sysfs_attributes(struct mem_ctl_info *mci)
+{
+ sysfs_remove_group(&mci->dev.kobj, &xsem_edac_sysfs_attr_group);
+}
+
static int mc_probe(struct platform_device *pdev)
{
- void __iomem *ddrmc_baseaddr, *ddrmc_noc_baseaddr;
+ void __iomem *ddrmc_baseaddr, *ddrmc_noc_baseaddr, *sem_baseaddr;
struct edac_mc_layer layers[2];
struct mem_ctl_info *mci;
u8 num_chans, num_csrows;
struct edac_priv *priv;
u32 edac_mc_id, regval;
+ u32 family_code;
int rc;
ddrmc_baseaddr = devm_platform_ioremap_resource_byname(pdev, "base");
@@ -1094,6 +2365,10 @@ static int mc_probe(struct platform_device *pdev)
if (!get_ecc_state(ddrmc_baseaddr))
return -ENXIO;
+ sem_baseaddr = devm_platform_ioremap_resource_byname(pdev, "semrtca");
+ if (IS_ERR(sem_baseaddr))
+ return PTR_ERR(sem_baseaddr);
+
/* Allocate ID number for the EMIF controller */
edac_mc_id = emif_get_id(pdev->dev.of_node);
@@ -1124,9 +2399,29 @@ static int mc_probe(struct platform_device *pdev)
priv = mci->pvt_info;
priv->ddrmc_baseaddr = ddrmc_baseaddr;
priv->ddrmc_noc_baseaddr = ddrmc_noc_baseaddr;
+ priv->sem_baseaddr = sem_baseaddr;
priv->ce_cnt = 0;
priv->ue_cnt = 0;
priv->mc_id = edac_mc_id;
+ priv->xsem_rtca = NULL;
+
+ /* Allocate and initialize XilSem RTCA structure */
+ priv->xsem_rtca = devm_kzalloc(&pdev->dev,
+ sizeof(struct xsem_rtca_priv),
+ GFP_KERNEL);
+ if (!priv->xsem_rtca) {
+ edac_printk(KERN_ERR, EDAC_MC,
+ "Failed to allocate xsem_rtca\n");
+ rc = -ENOMEM;
+ goto free_edac_mc;
+ }
+
+ priv->xsem_rtca->slr_info = devm_kzalloc(&pdev->dev, sizeof(struct xsem_ssit_status),
+ GFP_KERNEL);
+ if (!priv->xsem_rtca->slr_info) {
+ rc = -ENOMEM;
+ goto free_edac_mc;
+ }
mc_init(mci, pdev);
@@ -1147,6 +2442,41 @@ static int mc_probe(struct platform_device *pdev)
goto del_mc;
}
+ /* Create XilSem sysfs attributes only if XilSem is available */
+ rc = xsem_edac_create_sysfs_attributes(mci);
+ if (rc) {
+ edac_printk(KERN_ERR, EDAC_MC,
+ "Failed to create sysfs entries\n");
+ goto remove_sysfs;
+ }
+
+ /*
+ * Firmware driver returns -ENODEV if it is not probed. In this case
+ * defer XilSEM error event registration.
+ */
+ rc = zynqmp_pm_get_family_info(&family_code);
+ if (rc) {
+ if (rc == -ENODEV)
+ rc = -EPROBE_DEFER;
+
+ goto del_mc;
+ }
+ if (family_code == PM_VERSAL_FAMILY_CODE) {
+ priv->xsem_rtca->sw_event_node_id = VERSAL_EVENT_ERROR_SW_ERR;
+ priv->xsem_rtca->cram_ce_mask = XPM_VERSAL_EVENT_ERROR_MASK_XSEM_CRAM_CE_5;
+ priv->xsem_rtca->cram_ue_mask = XPM_VERSAL_EVENT_ERROR_MASK_XSEM_CRAM_UE_6;
+ priv->xsem_rtca->npi_ue_mask = XPM_VERSAL_EVENT_ERROR_MASK_XSEM_NPI_UE_7;
+ } else {
+ edac_printk(KERN_ERR, EDAC_MC, "Invalid Device family code %d\n", family_code);
+ }
+
+ rc = xlnx_register_event(PM_NOTIFY_CB, priv->xsem_rtca->sw_event_node_id,
+ priv->xsem_rtca->cram_ce_mask | priv->xsem_rtca->cram_ue_mask |
+ priv->xsem_rtca->npi_ue_mask,
+ false, xsem_err_callback, mci);
+ if (rc)
+ goto del_mc;
+
#ifdef CONFIG_EDAC_DEBUG
create_debugfs_attributes(mci);
setup_address_map(priv);
@@ -1154,6 +2484,8 @@ static int mc_probe(struct platform_device *pdev)
enable_intr(priv);
return rc;
+remove_sysfs:
+ xsem_edac_remove_sysfs_attributes(mci);
del_mc:
edac_mc_del_mc(&pdev->dev);
free_edac_mc:
@@ -1173,9 +2505,21 @@ static void mc_remove(struct platform_device *pdev)
debugfs_remove_recursive(priv->debugfs);
#endif
+ /* Unregister XilSem events if they were registered */
+ if (priv->xsem_rtca) {
+ xlnx_unregister_event(PM_NOTIFY_CB, priv->xsem_rtca->sw_event_node_id,
+ priv->xsem_rtca->cram_ce_mask |
+ priv->xsem_rtca->cram_ue_mask |
+ priv->xsem_rtca->npi_ue_mask,
+ xsem_err_callback, mci);
+ }
xlnx_unregister_event(PM_NOTIFY_CB, VERSAL_EVENT_ERROR_PMC_ERR1,
XPM_EVENT_ERROR_MASK_DDRMC_CR |
XPM_EVENT_ERROR_MASK_DDRMC_NCR, err_callback, mci);
+ /* Remove XilSem sysfs attributes if they were created */
+ if (priv->xsem_rtca)
+ xsem_edac_remove_sysfs_attributes(mci);
+
edac_mc_del_mc(&pdev->dev);
edac_mc_free(mci);
}
--
2.23.0
^ permalink raw reply related [flat|nested] 11+ messages in thread