From: sashiko-bot@kernel.org
To: "Luca Leonardo Scorcia" <l.scorcia@gmail.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org
Subject: Re: [RFC PATCH 3/3] arm64: dts: mt8516/mt8167: Update pinctrl nodes for the new paris driver
Date: Thu, 25 Jun 2026 11:07:08 +0000 [thread overview]
Message-ID: <20260625110709.417AC1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260625104742.113803-4-l.scorcia@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `gpio-ranges` property incorrectly specifies a count of 124, which excludes the final pin (GPIO 124) from being mapped to the GPIO subsystem, as the drivers define exactly 125 pins.
--
commit 36a8d0bd5d2cccdc70b499936029deb0499393de
Author: Luca Leonardo Scorcia <l.scorcia@gmail.com>
arm64: dts: mt8516/mt8167: Update pinctrl nodes for the new paris driver
This patch updates the MediaTek mt8516 and mt8167 SoC descriptions to
respect the constraints of the Paris pinctrl driver. It sets separate base
and eint registers and removes the deprecated syscfg_pctl syscon node.
> diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
> index b5e753759465d..63f36df4d1b48 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
[ ... ]
> @@ -231,17 +231,13 @@ keypad: keypad@10002000 {
> status = "disabled";
> };
>
> - syscfg_pctl: syscfg-pctl@10005000 {
> - compatible = "syscon";
> - reg = <0 0x10005000 0 0x1000>;
> - };
> -
> - pio: pinctrl@1000b000 {
> + pio: pinctrl@10005000 {
> compatible = "mediatek,mt8516-pinctrl";
> - reg = <0 0x1000b000 0 0x1000>;
> - mediatek,pctl-regmap = <&syscfg_pctl>;
> + reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
> + reg-names = "base", "eint";
> gpio-controller;
> #gpio-cells = <2>;
> + gpio-ranges = <&pio 0 0 124>;
[Severity: Medium]
Does this count parameter accidentally exclude the final pin (GPIO 124) from
being mapped to the GPIO subsystem?
Looking at the driver definitions for the MT8516 and MT8167 platforms, there
are exactly 125 pins defined. A count of 124 will prevent the mapping of the
final pin, causing any driver or application attempting to request GPIO 124 to
fail. Since mt8167.dtsi includes mt8516.dtsi, this affects both SoCs.
Should this count parameter be 125 instead?
> interrupt-controller;
> #interrupt-cells = <2>;
> interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260625104742.113803-1-l.scorcia@gmail.com?part=3
prev parent reply other threads:[~2026-06-25 11:07 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-25 10:46 [RFC PATCH 0/3] pinctrl: mediatek: mt8516-mt8167: Convert to Paris driver Luca Leonardo Scorcia
2026-06-25 10:46 ` [RFC PATCH 1/3] dt-bindings: pinctrl: mt8516/mt8167: Move compatibles from mt66xx to mt6795 Luca Leonardo Scorcia
2026-06-25 11:04 ` sashiko-bot
2026-06-25 10:46 ` [RFC PATCH 2/3] pinctrl: mediatek: mt8516/mt8167: Migrate driver to pinctrl-paris platform Luca Leonardo Scorcia
2026-06-25 11:16 ` sashiko-bot
2026-06-25 10:46 ` [RFC PATCH 3/3] arm64: dts: mt8516/mt8167: Update pinctrl nodes for the new paris driver Luca Leonardo Scorcia
2026-06-25 11:07 ` sashiko-bot [this message]
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