From: sashiko-bot@kernel.org
To: "Dinh Nguyen" <dinguyen@kernel.org>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2
Date: Fri, 26 Jun 2026 04:31:46 +0000 [thread overview]
Message-ID: <20260626043146.961401F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260626042541.1091774-2-dinguyen@kernel.org>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incomplete DT update: gmac0 is left with an invalid interrupt count that will fail dtbs validation.
--
commit ce31f4c657e3508e9aef68e6da54a09c1d243026
Author: Dinh Nguyen <dinguyen@kernel.org>
arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2
Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue
pairs.
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 02e62d954e949..140e4bf9fb155 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -670,8 +670,40 @@ gmac1: ethernet@10820000 {
> compatible = "altr,socfpga-stmmac-agilex5",
> "snps,dwxgmac-2.10";
> reg = <0x10820000 0x3500>;
[Severity: Medium]
Should gmac0 also be updated to include 17 interrupts?
Looking earlier in the same file, gmac0 uses the exact same
"altr,socfpga-stmmac-agilex5" compatible string, but this patch
leaves it configured with only a single interrupt:
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi:
gmac0: ethernet@10810000 {
compatible = "altr,socfpga-stmmac-agilex5",
"snps,dwxgmac-2.10";
reg = <0x10810000 0x3500>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
...
}
Since the device tree binding strictly requires 17 interrupts for this
specific compatible string, won't skipping gmac0 result in dtbs_check
validation errors and leave its queues without dedicated interrupts at
runtime?
> - interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "macirq";
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260626042541.1091774-1-dinguyen@kernel.org?part=2
next prev parent reply other threads:[~2026-06-26 4:31 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-26 4:25 [PATCH 1/2] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 Dinh Nguyen
2026-06-26 4:25 ` [PATCH 2/2] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2 Dinh Nguyen
2026-06-26 4:31 ` sashiko-bot [this message]
2026-06-26 10:53 ` Dinh Nguyen
2026-06-26 4:31 ` [PATCH 1/2] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 sashiko-bot
2026-06-26 16:08 ` Conor Dooley
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