* [PATCH 2/2] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2
2026-06-26 4:25 [PATCH 1/2] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 Dinh Nguyen
@ 2026-06-26 4:25 ` Dinh Nguyen
2026-06-26 4:31 ` sashiko-bot
2026-06-26 4:31 ` [PATCH 1/2] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 sashiko-bot
2026-06-26 16:08 ` Conor Dooley
2 siblings, 1 reply; 6+ messages in thread
From: Dinh Nguyen @ 2026-06-26 4:25 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt
Cc: dinguyen, devicetree, muhammad.nazim.amirul.nazle.asmade
Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue
pairs.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
.../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 72 +++++++++++++++++--
1 file changed, 68 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 2096decb5655..f54767d1526e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -702,8 +702,40 @@ gmac1: ethernet@10820000 {
compatible = "altr,socfpga-stmmac-agilex5",
"snps,dwxgmac-2.10";
reg = <0x10820000 0x3500>;
- interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "tx-queue-0",
+ "tx-queue-1",
+ "tx-queue-2",
+ "tx-queue-3",
+ "tx-queue-4",
+ "tx-queue-5",
+ "tx-queue-6",
+ "tx-queue-7",
+ "rx-queue-0",
+ "rx-queue-1",
+ "rx-queue-2",
+ "rx-queue-3",
+ "rx-queue-4",
+ "rx-queue-5",
+ "rx-queue-6",
+ "rx-queue-7";
resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr AGILEX5_EMAC1_CLK>,
@@ -816,8 +848,40 @@ gmac2: ethernet@10830000 {
compatible = "altr,socfpga-stmmac-agilex5",
"snps,dwxgmac-2.10";
reg = <0x10830000 0x3500>;
- interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "tx-queue-0",
+ "tx-queue-1",
+ "tx-queue-2",
+ "tx-queue-3",
+ "tx-queue-4",
+ "tx-queue-5",
+ "tx-queue-6",
+ "tx-queue-7",
+ "rx-queue-0",
+ "rx-queue-1",
+ "rx-queue-2",
+ "rx-queue-3",
+ "rx-queue-4",
+ "rx-queue-5",
+ "rx-queue-6",
+ "rx-queue-7";
resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
--
2.42.0.411.g813d9a9188
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 1/2] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5
2026-06-26 4:25 [PATCH 1/2] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 Dinh Nguyen
2026-06-26 4:25 ` [PATCH 2/2] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2 Dinh Nguyen
@ 2026-06-26 4:31 ` sashiko-bot
2026-06-26 16:08 ` Conor Dooley
2 siblings, 0 replies; 6+ messages in thread
From: sashiko-bot @ 2026-06-26 4:31 UTC (permalink / raw)
To: Dinh Nguyen; +Cc: conor+dt, devicetree, robh
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Removing the top-level constraints for `interrupts` and `interrupt-names` without restoring them in the `else` block allows older variants to incorrectly pass schema validation with up to 17 interrupts.
--
commit b9bb703e842480b5efde889d362af4d3e53520cb
Author: Dinh Nguyen <dinguyen@kernel.org>
dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5
The stmmac hardware on Agilex5 supports 8 TX/RX queue pairs and is
dma-coherent. This commit updates the schema to handle the hardware
differences between SoC variants.
> diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
> index fc445ad5a1f1a..9bae17688992c 100644
> --- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
> +++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
[ ... ]
> @@ -62,12 +62,28 @@ properties:
> - const: stmmaceth
> - const: ptp_ref
>
> - interrupts:
> - maxItems: 1
> -
> interrupt-names:
[ ... ]
> @@ -149,10 +165,35 @@ required:
[ ... ]
> allOf:
> - $ref: snps,dwmac.yaml#
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: altr,socfpga-stmmac-agilex5
> + then:
> + properties:
> + interrupts:
> + minItems: 17
> + maxItems: 17
> +
> + interrupt-names:
> + minItems: 17
> + maxItems: 17
> +
> + dma-coherent: true
> + else:
> + properties:
> + interrupts:
> + minItems: 1
[Severity: Medium]
Does this missing maxItems constraint allow older variants to incorrectly pass
schema validation with up to 17 interrupts?
Since the top-level maxItems: 1 constraint was removed for interrupts, this
else block applies to all non-Agilex5 variants but only enforces minItems: 1.
Because there are no top-level restrictions stopping it, device trees for
older variants (e.g., altr,socfpga-stmmac-a10-s10) could specify multiple
interrupts and matching interrupt-names without triggering a schema validation
error.
Should maxItems: 1 for interrupts and a matching constraint for
interrupt-names be added to this else block to enforce the original strict
hardware constraints for prior generations?
> +
> + dma-coherent: false
> +
> unevaluatedProperties: false
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260626042541.1091774-1-dinguyen@kernel.org?part=1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5
2026-06-26 4:25 [PATCH 1/2] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 Dinh Nguyen
2026-06-26 4:25 ` [PATCH 2/2] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2 Dinh Nguyen
2026-06-26 4:31 ` [PATCH 1/2] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 sashiko-bot
@ 2026-06-26 16:08 ` Conor Dooley
2 siblings, 0 replies; 6+ messages in thread
From: Conor Dooley @ 2026-06-26 16:08 UTC (permalink / raw)
To: Dinh Nguyen
Cc: robh, krzk+dt, conor+dt, devicetree,
muhammad.nazim.amirul.nazle.asmade
[-- Attachment #1: Type: text/plain, Size: 2864 bytes --]
On Thu, Jun 25, 2026 at 11:25:40PM -0500, Dinh Nguyen wrote:
> The stmmac hardware on Agilex5 supports 8 TX/RX queue pairs and is
> dma-coherent. Update the schema to handle the hardware differences
> between SoC variants.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> .../bindings/net/altr,socfpga-stmmac.yaml | 51 +++++++++++++++++--
> 1 file changed, 46 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
> index fc445ad5a1f1..9bae17688992 100644
> --- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
> +++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
> @@ -62,12 +62,28 @@ properties:
> - const: stmmaceth
> - const: ptp_ref
>
> - interrupts:
> - maxItems: 1
> -
The top level should retain the widest constraints, so this should say
min 1 max 17.
> interrupt-names:
> - items:
> - - const: macirq
> + oneOf:
> + - items:
> + - const: macirq
This is unneeded, just have one list with everything, since entry 1 is
the same for both.
> + - items:
> + - const: macirq
> + - const: tx-queue-0
> + - const: tx-queue-1
> + - const: tx-queue-2
> + - const: tx-queue-3
> + - const: tx-queue-4
> + - const: tx-queue-5
> + - const: tx-queue-6
> + - const: tx-queue-7
> + - const: rx-queue-0
> + - const: rx-queue-1
> + - const: rx-queue-2
> + - const: rx-queue-3
> + - const: rx-queue-4
> + - const: rx-queue-5
> + - const: rx-queue-6
> + - const: rx-queue-7
>
> iommus:
> minItems: 1
> @@ -149,10 +165,35 @@ required:
> - clocks
> - clock-names
> - altr,sysmgr-syscon
> + - interrupts
> + - interrupt-names
No mention in the commit message of an ABI change.
>
> allOf:
> - $ref: snps,dwmac.yaml#
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: altr,socfpga-stmmac-agilex5
> + then:
> + properties:
> + interrupts:
> + minItems: 17
> + maxItems: 17
With the change I suggest for the list, the maxItems here can be
removed.
> +
> + interrupt-names:
> + minItems: 17
> + maxItems: 17
And here.
> +
> + dma-coherent: true
> + else:
> + properties:
> + interrupts:
> + minItems: 1
This should have been maxItems: 1 I think.
pw-bot: changes-requested
Thanks,
Conor.
> +
> + dma-coherent: false
> +
> unevaluatedProperties: false
>
> examples:
> --
> 2.42.0.411.g813d9a9188
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread