[RFC v3 PATCH 0/2] Add Lenovo ThinkEdge SE70 carrier board support

[RFC v3 PATCH 0/2] Add Lenovo ThinkEdge SE70 carrier board support

[Jiqi Li]

This patch set introduces device tree binding and standalone DTS file
for Lenovo ThinkEdge SE70, a fanless industrial edge gateway powered by
NVIDIA Tegra194 (Xavier NX P3509-0000 + P3668-0001) SOM.

Patch 1 updates tegra.yaml bindings to add three-stage compatible string
matching board + SOM + SoC, aligning with existing Tegra carrier board specs.
Patch 2 adds full compliant carrier DTS implementing 40-pin header pinmux,
400kHz I2C bus, dedicated SD card 3.3V power regulator; disables unpopulated
PWM/tach hardware per real hardware layout.

All static device tree checks pass: dtbs compile, dt_binding_check complete
without failures.

We maintain internal downstream DTS for mass-production SE70 hardware.
Upstreaming follows the same OEM contribution pattern as Google/Xiaomi Tegra
boards, reduces long-term out-of-tree patch maintenance burden.
This industrial platform has a full 7-year production support lifecycle until
2028, Lenovo will continuously backport DT fixes throughout its service window.
All peripherals rely on generic mainline drivers, no proprietary extensions.

Changes in v3:
- Fix all Sashiko static DT violations:
  1. Reorganize pinctrl, put all pin configs under pinmux@2430000
  2. Rename sdhci@3440000 to mmc@3440000 to match upstream
  3. Move pwm-fan disable node to root level
  4. Remove disabled overrides for non-existent nodes
  5. Drop unused #address-cells / #size-cells from fixed-regulators
- Extend compatible string to board+SOM+tegra194 triple format

Jiqi Li (2):
  dt-bindings: arm: tegra: Add lenovo,thinkedge-se70 compatible string
  arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

 .../devicetree/bindings/arm/tegra.yaml        |   5 +
 arch/arm64/boot/dts/nvidia/Makefile           |   1 +
 .../nvidia/tegra194-lenovo-thinkedge-se70.dts | 124 ++++++++++++++++++
 3 files changed, 130 insertions(+)
 create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts

-- 
2.43.0

[PATCH 1/2] dt-bindings: arm: tegra: Add lenovo,thinkedge-se70 compatible string

[Jiqi Li]

Lenovo ThinkEdge SE70 is a fanless industrial edge gateway carrier
board based on NVIDIA Tegra194 (Xavier NX) SOM.
Add the corresponding compatible string for device tree validation.

Signed-off-by: Jiqi Li <lijq9@lenovo.com>
---
 Documentation/devicetree/bindings/arm/tegra.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml
index 033a63f6c068..1a71b4195114 100644
--- a/Documentation/devicetree/bindings/arm/tegra.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra.yaml
@@ -268,6 +268,11 @@ properties:
         items:
           - const: nvidia,p3509-0000+p3668-0001
           - const: nvidia,tegra194
+      - description: Lenovo ThinkEdge SE70
+        items:
+          - const: lenovo,thinkedge-se70
+          - const: nvidia,p3509-0000+p3668-0001
+          - const: nvidia,tegra194
       - items:
           - const: nvidia,tegra234-vdk
           - const: nvidia,tegra234
-- 
2.43.0

[PATCH 2/2] arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

[Jiqi Li]

ThinkEdge SE70 is a fanless industrial edge gateway built around
NVIDIA Tegra194 Xavier NX SOM. This patch adds a standalone device
tree file describing core carrier board peripherals:
- Custom 40-pin header pinmux configuration
- External SD card slot with dedicated 3.3V fixed regulator

No fan, PWM, tachometer, extra camera/spi peripherals are present
on this passively cooled platform, so unused nodes are explicitly
disabled following mainline device tree best practices.

Static verification passed: dt_binding_check and dtbs compilation
complete without errors.

Signed-off-by: Jiqi Li <lijq9@lenovo.com>
---
 arch/arm64/boot/dts/nvidia/Makefile           |   1 +
 .../nvidia/tegra194-lenovo-thinkedge-se70.dts | 124 ++++++++++++++++++
 2 files changed, 125 insertions(+)
 create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts

diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index 72c0cb5efa47..736a3f8a923f 100644
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p3509-0000+p3636-0001.dtb
 dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb
+dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-lenovo-thinkedge-se70.dtb
 dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb
 dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0008.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
new file mode 100644
index 000000000000..44a7ae9a05bf
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra194-p3668-0001.dtsi"
+#include "tegra194-p3509-0000.dtsi"
+
+/ {
+	model = "Lenovo ThinkEdge SE70";
+	compatible = "lenovo,thinkedge-se70", "nvidia,p3509-0000+p3668-0001", "nvidia,tegra194";
+
+	chosen {
+		bootargs = "console=ttyTCU0,115200";
+	};
+
+	/* Fixed 3.3V regulator for external SD card slot */
+	fixed-regulators {
+		compatible = "simple-bus";
+		ap2306gn_3v3_sd: ap2306gn-3v3-sd {
+			compatible = "regulator-fixed";
+			regulator-name = "ap2306gn-3v3-sd";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio TEGRA194_MAIN_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			status = "okay";
+		};
+	};
+
+	bus@0 {
+
+		/* Custom pinmux configurations for 40-pin expansion header */
+		pinmux@2430000 {
+			status = "okay";
+			pinctrl-names = "default";
+			pinctrl-0 = <&hdr40_pinmux>;
+
+			hdr40_pinmux: header-40pin-pinmux {
+				pin7 {
+					nvidia,pins = "aud_mclk_ps4";
+					nvidia,function = "aud";
+					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				pin11 {
+					nvidia,pins = "uart1_rts_pr4";
+					nvidia,function = "uarta";
+					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				pin12 {
+					nvidia,pins = "dap5_sclk_pt5";
+					nvidia,function = "i2s5";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				pin35 {
+					nvidia,pins = "dap5_fs_pu0";
+					nvidia,function = "i2s5";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				pin36 {
+					nvidia,pins = "uart1_cts_pr5";
+					nvidia,function = "uarta";
+					nvidia,pull = <TEGRA_PIN_PULL_UP>;
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				pin38 {
+					nvidia,pins = "dap5_din_pt7";
+					nvidia,function = "i2s5";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				pin40 {
+					nvidia,pins = "dap5_dout_pt6";
+					nvidia,function = "i2s5";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+			};
+		};
+
+		/* Configure i2c bus clock to 400kHz for carrier board peripherals */
+		i2c@3160000 {
+			clock-frequency = <400000>;
+			status = "okay";
+		};
+
+		/* SDMMC3 for external user SD card slot with dedicated 3.3V power */
+		mmc@3440000 {
+			vmmc-supply = <&ap2306gn_3v3_sd>;
+			cd-gpios = <&gpio_aon TEGRA194_AON_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
+			status = "okay";
+		};
+
+		pwm@c340000 {
+			status = "disabled";
+		};
+		pwm@3280000 {
+			status = "disabled";
+		};
+		pwm@32c0000 {
+			status = "disabled";
+		};
+		pwm@32d0000 {
+			status = "disabled";
+		};
+		pwm@32f0000 {
+			status = "disabled";
+		};
+	};
+
+	/* Disable fan hardware not populated on SE70 carrier board */
+	pwm-fan {
+		status = "disabled";
+	};
+};
-- 
2.43.0

Re: [PATCH 2/2] arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [High] Missing `no-1-8-v` property or 1.8V-capable `vqmmc-supply` for `mmc@3440000` while UHS modes are enabled in the base DTSI.
- [High] Missing `bus-width` property for the SD card slot (`mmc@3440000`).
- [Medium] Device tree schema violation for 'fixed-regulators' wrapper and its child node.
- [Medium] The patch fails to disable the unused SPI peripheral as claimed in the commit message.
- [Medium] Missing `disable-wp` property in the SD card node (`mmc@3440000`).
--

commit d7f4007a1b474f4e8527dff37fcaa0da82f91d42
Author: Jiqi Li <lijq9@lenovo.com>

arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

ThinkEdge SE70 is a fanless industrial edge gateway built around
NVIDIA Tegra194 Xavier NX SOM. This patch adds a standalone device
tree file describing core carrier board peripherals.

> No fan, PWM, tachometer, extra camera/spi peripherals are present
> on this passively cooled platform, so unused nodes are explicitly
> disabled following mainline device tree best practices.

[Severity: Medium]
Does this patch actually disable the extra SPI peripherals as claimed?

The tegra194-p3509-0000.dtsi explicitly enables the spi@3270000 node, but
there doesn't appear to be an override to disable it in this file. The
unpopulated SPI flash driver will probe on boot and waste resources.

> diff --git a/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
> new file mode 100644
> index 0000000000000..44a7ae9a05bfb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts

[ ... ]

> @@ -14,6 +14,6 @@
> +	/* Fixed 3.3V regulator for external SD card slot */
> +	fixed-regulators {
> +		compatible = "simple-bus";
> +		ap2306gn_3v3_sd: ap2306gn-3v3-sd {
> +			compatible = "regulator-fixed";
> +			regulator-name = "ap2306gn-3v3-sd";

[Severity: Medium]
Does this fixed-regulators node comply with the device tree schemas?

Using simple-bus requires the #address-cells, #size-cells, and ranges
properties, which are missing here. Additionally, the ap2306gn-3v3-sd child
node does not start with the regulator- prefix as required by the
fixed-regulator.yaml schema.

This seems to contradict the commit message claim that dt_binding_check
passed without errors.

[ ... ]

> @@ -95,6 +95,6 @@
> +		/* SDMMC3 for external user SD card slot with dedicated 3.3V power */
> +		mmc@3440000 {
> +			vmmc-supply = <&ap2306gn_3v3_sd>;
> +			cd-gpios = <&gpio_aon TEGRA194_AON_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
> +			status = "okay";
> +		};

[Severity: High]
Does this configuration need a no-1-8-v property or a 1.8V-capable
vqmmc-supply?

The tegra194.dtsi enables UHS-I modes for mmc@3440000, which require 1.8V
signaling. Since this node only defines a fixed 3.3V supply without disabling
1.8V modes, won't the MMC core try to switch the SoC pads to 1.8V signaling
while the card is powered at 3.3V? This could cause I/O failures and
hardware overstress.

[Severity: High]
Should this node specify a bus-width property?

If the bus-width property is omitted, the MMC subsystem defaults to 1-bit
mode. Since the parent sdmmc3 node in tegra194.dtsi does not specify a
bus-width, will this SD card operate in a degraded 1-bit mode, artificially
crippling read and write performance?

[Severity: Medium]
Could this node be missing a disable-wp property?

If the board leaves the internal WP pin floating and disable-wp is absent,
could the kernel randomly mount the SD card as read-only?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260626091349.570091-1-lijq9@lenovo.com?part=2

[RFC v4 PATCH 0/2] Add Lenovo ThinkEdge SE70 carrier board support

[Jiqi Li]

This patch set introduces device tree binding and standalone DTS file
for Lenovo ThinkEdge SE70, a fanless industrial edge gateway powered by
NVIDIA Tegra194 (Xavier NX P3509-0000 + P3668-0001) SOM.

Patch 1 updates tegra.yaml bindings to add three-stage compatible string
matching board + SOM + SoC, aligning with existing Tegra carrier board specs.
Patch 2 adds a fully compliant carrier board DTS implementing 40-pin header
pinmux configuration, 400kHz I2C bus, and dedicated 3.3V SD-card regulator.
It also disables unpopulated PWM, fan, and SPI peripherals according to the
real hardware layout.

All static device tree checks pass: dtbs compile and dt_binding_check
complete without local errors. Pre-existing upstream DTSI warnings are
inherited and unrelated to this board addition.

We maintain internal downstream DTS for mass-production SE70 hardware.
Upstreaming follows the same OEM contribution pattern as other Tegra
carrier boards from Google and Xiaomi, reducing long-term out-of-tree
maintenance burden. This industrial platform has a 7-year production
lifecycle until 2028, and Lenovo will continuously backport DT fixes
during its service window. All peripherals use generic mainline drivers
with no proprietary extensions.

Changes in v4:
- Fix pinctrl subnode naming to comply with tegra194 pinmux schema regex rules
- Rework SD regulator implementation: remove invalid simple-bus wrapper,
  adopt official NVIDIA P3668 regulator naming and add regulator-boot-on
- Fully comply with MMC binding requirements by adding bus-width = <4>,
  disable-wp, and no-1-8-v properties to SDMMC3 node
- Add explicit spi@3270000 disable override to align with commit description
- Resolve all remaining Sashiko medium/high static DT violations

Jiqi Li (2):
  dt-bindings: arm: tegra: Add lenovo,thinkedge-se70 compatible string
  arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

 .../devicetree/bindings/arm/tegra.yaml        |   5 +
 arch/arm64/boot/dts/nvidia/Makefile           |   1 +
 .../nvidia/tegra194-lenovo-thinkedge-se70.dts | 129 ++++++++++++++++++
 3 files changed, 135 insertions(+)
 create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts

-- 
2.43.0

[PATCH 2/2] arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

[Jiqi Li]

ThinkEdge SE70 is a fanless industrial edge gateway built around
NVIDIA Tegra194 Xavier NX SOM. This patch adds a standalone device
tree file describing core carrier board peripherals:
- Custom 40-pin header pinmux configuration
- External SD card slot with dedicated 3.3V fixed regulator

No fan, PWM, tachometer, extra camera/spi peripherals are present
on this passively cooled platform, so unused nodes are explicitly
disabled following mainline device tree best practices.

Static verification passed: dt_binding_check and dtbs compilation
complete without errors.

Signed-off-by: Jiqi Li <lijq9@lenovo.com>
---
 arch/arm64/boot/dts/nvidia/Makefile           |   1 +
 .../nvidia/tegra194-lenovo-thinkedge-se70.dts | 129 ++++++++++++++++++
 2 files changed, 130 insertions(+)
 create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts

diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index 72c0cb5efa47..736a3f8a923f 100644
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p3509-0000+p3636-0001.dtb
 dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb
+dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-lenovo-thinkedge-se70.dtb
 dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb
 dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0008.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
new file mode 100644
index 000000000000..47b770170507
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra194-p3668-0001.dtsi"
+#include "tegra194-p3509-0000.dtsi"
+
+/ {
+	model = "Lenovo ThinkEdge SE70";
+	compatible = "lenovo,thinkedge-se70", "nvidia,p3509-0000+p3668-0001", "nvidia,tegra194";
+
+	chosen {
+		bootargs = "console=ttyTCU0,115200";
+	};
+
+	/* Fixed 3.3V regulator for external SD card slot */
+	vdd_3v3_sd: regulator-sd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_3V3_SD";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio TEGRA194_MAIN_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+		enable-active-high;
+		status = "okay";
+	};
+
+	bus@0 {
+
+		/* Custom pinmux configurations for 40-pin expansion header */
+		pinmux@2430000 {
+			status = "okay";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinmux_hdr40>;
+
+			pinmux_hdr40: pinmux-hdr40 {
+				pin7 {
+					nvidia,pins = "aud_mclk_ps4";
+					nvidia,function = "aud";
+					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				pin11 {
+					nvidia,pins = "uart1_rts_pr4";
+					nvidia,function = "uarta";
+					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				pin12 {
+					nvidia,pins = "dap5_sclk_pt5";
+					nvidia,function = "i2s5";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				pin35 {
+					nvidia,pins = "dap5_fs_pu0";
+					nvidia,function = "i2s5";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				pin36 {
+					nvidia,pins = "uart1_cts_pr5";
+					nvidia,function = "uarta";
+					nvidia,pull = <TEGRA_PIN_PULL_UP>;
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				pin38 {
+					nvidia,pins = "dap5_din_pt7";
+					nvidia,function = "i2s5";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				pin40 {
+					nvidia,pins = "dap5_dout_pt6";
+					nvidia,function = "i2s5";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+			};
+		};
+
+		/* Configure i2c bus clock to 400kHz for carrier board peripherals */
+		i2c@3160000 {
+			clock-frequency = <400000>;
+			status = "okay";
+		};
+
+		/* SDMMC3 for external user SD card slot with dedicated 3.3V power */
+		mmc@3440000 {
+			bus-width = <4>;
+			cd-gpios = <&gpio_aon TEGRA194_AON_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
+			disable-wp;
+			no-1-8-v;
+			vmmc-supply = <&vdd_3v3_sd>;
+			status = "okay";
+		};
+
+		pwm@c340000 {
+			status = "disabled";
+		};
+		pwm@3280000 {
+			status = "disabled";
+		};
+		pwm@32c0000 {
+			status = "disabled";
+		};
+		pwm@32d0000 {
+			status = "disabled";
+		};
+		pwm@32f0000 {
+			status = "disabled";
+		};
+
+		spi@3270000 {
+			status = "disabled";
+		};
+	};
+
+	/* Disable fan hardware not populated on SE70 carrier board */
+	pwm-fan {
+		status = "disabled";
+	};
+};
-- 
2.43.0

Re: [PATCH 2/2] arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The device tree erroneously disables the QSPI NOR flash controller (`spi@3270000`), breaking OS-level access to the SOM's boot firmware.
--

commit 0ad71e09cd3382aee8aca7f31b76da55ec8f3499
Author: Jiqi Li <lijq9@lenovo.com>

arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

This commit adds a standalone device tree file for the Lenovo ThinkEdge
SE70 carrier board, which is based on the NVIDIA Tegra194 Xavier NX SOM.
It configures the 40-pin header pinmux, an external SD card slot, and
disables unused PWM and SPI nodes to reflect the passively cooled platform.

> diff --git a/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
> new file mode 100644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
[ ... ]
> +		pwm@32f0000 {
> +			status = "disabled";
> +		};
> +
> +		spi@3270000 {
> +			status = "disabled";
> +		};

[Severity: Medium]
Will disabling spi@3270000 break OS-level access to the SOM's boot firmware? 

This overrides the 'okay' status inherited from the carrier board DTSI,
disabling the QSPI controller needed to access the internal SPI NOR flash.
Without this controller, userspace tools may be permanently prevented from
updating the bootloader or firmware.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260626105625.600156-1-lijq9@lenovo.com?part=2

[RFC v2 PATCH 0/2] Add Lenovo ThinkEdge SE70 carrier board support

[Jiqi Li]

This series adds device tree bindings and standalone DTS for the Lenovo
ThinkEdge SE70 fanless industrial edge gateway based on NVIDIA Tegra194
Xavier NX SOM.

Patch 1 adds the board compatible string to tegra.yaml for dt-schema
validation.
Patch 2 introduces the carrier board DTS with 40-pin header pinmux and
external SD card power regulator, disables unused fan/PWM/spi peripherals.

Static verification passed: dt_binding_check and dtbs compilation
complete without errors.

We maintain downstream DTS for mass-deployed SE70 hardware internally.
Upstreaming aligns with existing OEM board contributions (Google/Xiaomi)
in the Tegra tree, cuts long-term out-of-tree patch maintenance overhead.
This industrial platform has a full 7-year support lifecycle until 2028;
Lenovo will keep backporting DT fixes throughout its service window.
All peripherals use generic upstream drivers with no proprietary extensions.


Changes in v2:
- Wrap all memory-mapped peripherals under root bus@0 node to match upstream
  tegra194.dtsi hardware topology
- Add missing tegra194.dtsi include to resolve undefined GPIO/pinctrl macros
- Fix regulator label syntax error (illegal hyphens replaced with underscores),
  sync supply reference in sdhci node
- Remove downstream L4T-only nvidia,lpdr pinmux property which lacks upstream binding
- Fix SD card detect double inversion logic: drop cd-inverted property,
  set cd-gpios to GPIO_ACTIVE_HIGH
- Add required simple-bus properties (#address-cells, #size-cells) to fixed-regulators
- Unify all node labels to underscore naming per devicetree specification
- Correct mismatched 2.3V -> 3.3V regulator comment
- Trim compound SOM compatible string to eliminate un-documented binding warning

Jiqi Li (2):
  dt-bindings: arm: tegra: Add lenovo,thinkedge-se70 compatible string
  arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

 .../devicetree/bindings/arm/tegra.yaml        |   4 +
 arch/arm64/boot/dts/nvidia/Makefile           |   1 +
 .../nvidia/tegra194-lenovo-thinkedge-se70.dts | 164 ++++++++++++++++++
 3 files changed, 169 insertions(+)
 create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts

-- 
2.43.0

[PATCH 2/2] arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

[Jiqi Li]

ThinkEdge SE70 is a fanless industrial edge gateway built around
NVIDIA Tegra194 Xavier NX SOM. This patch adds a standalone device
tree file describing core carrier board peripherals:
- Custom 40-pin header pinmux configuration
- External SD card slot with dedicated 3.3V fixed regulator

No fan, PWM, tachometer, extra camera/spi peripherals are present
on this passively cooled platform, so unused nodes are explicitly
disabled following mainline device tree best practices.

Static verification passed: dt_binding_check and dtbs compilation
complete without errors.

Signed-off-by: Jiqi Li <lijq9@lenovo.com>
---
 arch/arm64/boot/dts/nvidia/Makefile           |   1 +
 .../nvidia/tegra194-lenovo-thinkedge-se70.dts | 164 ++++++++++++++++++
 2 files changed, 165 insertions(+)
 create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts

diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index 72c0cb5efa47..736a3f8a923f 100644
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p3509-0000+p3636-0001.dtb
 dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb
+dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-lenovo-thinkedge-se70.dtb
 dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb
 dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0008.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
new file mode 100644
index 000000000000..d44eb7c9b474
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra194-p3668-0001.dtsi"
+#include "tegra194-p3509-0000.dtsi"
+
+/ {
+	model = "Lenovo ThinkEdge SE70";
+	compatible = "lenovo,thinkedge-se70", "nvidia,tegra194";
+
+	chosen {
+		bootargs = "console=ttyTCU0,115200";
+	};
+
+	/* Fixed 3.3V regulator for external SD card slot */
+	fixed-regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ap2306gn_3v3_sd: ap2306gn-3v3-sd {
+			compatible = "regulator-fixed";
+			regulator-name = "ap2306gn-3v3-sd";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio TEGRA194_MAIN_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			status = "okay";
+		};
+	};
+
+	bus@0 {
+
+		/* Custom pinmux configurations for 40-pin expansion header */
+		pinmux@c302000 {
+			status = "okay";
+			touch-clk-pcc4 {
+				nvidia,pins = "touch_clk_pcc4";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+		};
+
+		pinmux@2430028 {
+			status = "okay";
+			soc-gpio41-pq5 {
+				nvidia,pins = "soc_gpio41_pq5";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+		};
+
+		pinmux@2430000 {
+			status = "okay";
+			pinctrl-names = "default";
+			pinctrl-0 = <&hdr40_pinmux>;
+
+			hdr40_pinmux: header-40pin-pinmux {
+				pin7 {
+					nvidia,pins = "aud_mclk_ps4";
+					nvidia,function = "aud";
+					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				pin11 {
+					nvidia,pins = "uart1_rts_pr4";
+					nvidia,function = "uarta";
+					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				pin12 {
+					nvidia,pins = "dap5_sclk_pt5";
+					nvidia,function = "i2s5";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				pin35 {
+					nvidia,pins = "dap5_fs_pu0";
+					nvidia,function = "i2s5";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				pin36 {
+					nvidia,pins = "uart1_cts_pr5";
+					nvidia,function = "uarta";
+					nvidia,pull = <TEGRA_PIN_PULL_UP>;
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				pin38 {
+					nvidia,pins = "dap5_din_pt7";
+					nvidia,function = "i2s5";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				pin40 {
+					nvidia,pins = "dap5_dout_pt6";
+					nvidia,function = "i2s5";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+			};
+		};
+
+		/* Configure i2c bus clock to 400kHz for carrier board peripherals */
+		i2c@3160000 {
+			clock-frequency = <400000>;
+			status = "okay";
+		};
+
+		/* SDMMC3 for external user SD card slot with dedicated 3.3V power */
+		sdhci@3440000 {
+			vmmc-supply = <&ap2306gn_3v3_sd>;
+			cd-gpios = <&gpio_aon TEGRA194_AON_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
+			status = "okay";
+		};
+
+		/* Disable fan and tachometer hardware not populated on SE70 carrier board */
+		pwm-fan {
+			status = "disabled";
+		};
+		thermal-fan-est {
+			status = "disabled";
+		};
+		tachometer@39c0000 {
+			status = "disabled";
+		};
+		pwm@c340000 {
+			status = "disabled";
+		};
+		pwm@3280000 {
+			status = "disabled";
+		};
+		pwm@32c0000 {
+			status = "disabled";
+		};
+		pwm@32d0000 {
+			status = "disabled";
+		};
+		pwm@32f0000 {
+			status = "disabled";
+		};
+		generic-pwm-tachometer {
+			status = "disabled";
+		};
+
+		/* Disable unused SPI interfaces on 40-pin header */
+		spi@3210000 {
+			status = "disabled";
+		};
+		spi@3230000 {
+			status = "disabled";
+		};
+	};
+};
-- 
2.43.0

Re: [PATCH 2/2] arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [High] Pin configurations are instantiated as standalone dummy nodes instead of subnodes of the pinctrl controllers.
- [High] SD card controller override fails due to a node name mismatch (`sdhci` vs `mmc`).
- [High] The pwm-fan status override fails because it is incorrectly nested under bus@0.
- [Medium] Device tree contains dead overrides for non-existent downstream nodes.
- [Medium] The fixed-regulators node incorrectly uses simple-bus with `#address-cells = <1>` for a sizeless child.
--

commit 124a29c4818b88a33b77f6bc336c64c7bd9a06ec
Author: Jiqi Li <lijq9@lenovo.com>

arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

ThinkEdge SE70 is a fanless industrial edge gateway built around
NVIDIA Tegra194 Xavier NX SOM. This patch adds a standalone device
tree file describing core carrier board peripherals.

> diff --git a/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
> new file mode 100644
> index 0000000000000..d44eb7c9b4742
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts

[ ... ]

> +	/* Fixed 3.3V regulator for external SD card slot */
> +	fixed-regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		ap2306gn_3v3_sd: ap2306gn-3v3-sd {

[Severity: Medium]
The fixed-regulators node is marked as compatible = "simple-bus" and sets
#address-cells = <1>, but its child ap2306gn-3v3-sd does not have a unit
address or a reg property.

Since the simple-bus binding requires children to have a reg or ranges
property, will this cause dtbs_check validation to fail?

[ ... ]

> +	bus@0 {
> +
> +		/* Custom pinmux configurations for 40-pin expansion header */
> +		pinmux@c302000 {
> +			status = "okay";
> +			touch-clk-pcc4 {
> +				nvidia,pins = "touch_clk_pcc4";
> +				nvidia,function = "rsvd2";
> +				nvidia,pull = <TEGRA_PIN_PULL_UP>;
> +				nvidia,tristate = <TEGRA_PIN_ENABLE>;
> +				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
> +			};
> +		};
> +
> +		pinmux@2430028 {
> +			status = "okay";
> +			soc-gpio41-pq5 {

[Severity: High]
Is it intended to create standalone nodes at the exact register offsets of
the individual pins (pinmux@c302000 and pinmux@2430028), instead of placing
them as subnodes under the main pinctrl controllers (which reside at
pinmux@c300000 and pinmux@2430000 in tegra194.dtsi)?

Because they are standalone nodes and lack a pinctrl-0 reference, the pinctrl
driver won't parse them, which will cause these pinmux configurations to be
ignored.

[ ... ]

> +		/* SDMMC3 for external user SD card slot with dedicated 3.3V power */
> +		sdhci@3440000 {
> +			vmmc-supply = <&ap2306gn_3v3_sd>;
> +			cd-gpios = <&gpio_aon TEGRA194_AON_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
> +			status = "okay";
> +		};

[Severity: High]
In the upstream tegra194.dtsi, the SDMMC3 controller is defined as
mmc@3440000.

Does using sdhci@3440000 here create a new, inert dummy node instead of
overriding the existing mmc@3440000 node? This would leave the actual
controller in its default disabled state.

> +
> +		/* Disable fan and tachometer hardware not populated on SE70 carrier board */
> +		pwm-fan {
> +			status = "disabled";
> +		};

[Severity: High]
In tegra194-p3509-0000.dtsi, the pwm-fan node is located at the root of the
device tree (/pwm-fan).

Since this override is nested inside /bus@0/, doesn't this create a new dummy
node at /bus@0/pwm-fan while leaving the actual root /pwm-fan node enabled?

> +		thermal-fan-est {
> +			status = "disabled";
> +		};
> +		tachometer@39c0000 {
> +			status = "disabled";
> +		};

[Severity: Medium]
It looks like nodes such as thermal-fan-est, tachometer@39c0000,
generic-pwm-tachometer, spi@3210000, and spi@3230000 do not exist in the
upstream tegra194 device tree sources.

Does overriding them here just create new dummy disabled nodes instead of
affecting real hardware?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260626033418.520762-1-lijq9@lenovo.com?part=2

[RFC PATCH 0/2] Add Lenovo ThinkEdge SE70 carrier board support

[Jiqi Li]

This series adds device tree bindings and standalone DTS for the Lenovo
ThinkEdge SE70 fanless industrial edge gateway based on NVIDIA Tegra194
Xavier NX SOM.

Patch 1 adds the board compatible string to tegra.yaml for dt-schema
validation.
Patch 2 introduces the carrier board DTS with 40-pin header pinmux and
external SD card power regulator, disables unused fan/PWM/spi peripherals.

Static verification passed: dt_binding_check and dtbs compilation
complete without errors.

We maintain downstream DTS for mass-deployed SE70 hardware internally.
Upstreaming aligns with existing OEM board contributions (Google/Xiaomi)
in the Tegra tree, cuts long-term out-of-tree patch maintenance overhead.
This industrial platform has a full 7-year support lifecycle until 2028;
Lenovo will keep backporting DT fixes throughout its service window.
All peripherals use generic upstream drivers with no proprietary extensions.

Jiqi Li (2):
  dt-bindings: arm: tegra: Add lenovo,thinkedge-se70 compatible string
  arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

 .../devicetree/bindings/arm/tegra.yaml        |   4 +
 arch/arm64/boot/dts/nvidia/Makefile           |   1 +
 .../nvidia/tegra194-lenovo-thinkedge-se70.dts | 167 ++++++++++++++++++
 3 files changed, 172 insertions(+)
 create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts

-- 
2.43.0

[PATCH 2/2] arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

[Jiqi Li]

ThinkEdge SE70 is a fanless industrial edge gateway built around
NVIDIA Tegra194 Xavier NX SOM. This patch adds a standalone device
tree file describing core carrier board peripherals:
- Custom 40-pin header pinmux configuration
- External SD card slot with dedicated 3.3V fixed regulator

No fan, PWM, tachometer, extra camera/spi peripherals are present
on this passively cooled platform, so unused nodes are explicitly
disabled following mainline device tree best practices.

Static verification passed: dt_binding_check and dtbs compilation
complete without errors.

Signed-off-by: Jiqi Li <lijq9@lenovo.com>
---
 arch/arm64/boot/dts/nvidia/Makefile           |   1 +
 .../nvidia/tegra194-lenovo-thinkedge-se70.dts | 167 ++++++++++++++++++
 2 files changed, 168 insertions(+)
 create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts

diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index 72c0cb5efa47..736a3f8a923f 100644
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p3509-0000+p3636-0001.dtb
 dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb
+dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-lenovo-thinkedge-se70.dtb
 dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb
 dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb
 dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0008.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
new file mode 100644
index 000000000000..075e057c9095
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra194-p3668-0001.dtsi"
+#include "tegra194-p3509-0000.dtsi"
+
+/ {
+	model = "Lenovo ThinkEdge SE70";
+	compatible = "lenovo,thinkedge-se70", "nvidia,p3509-0000+p3668-0001", "nvidia,tegra194";
+
+	chosen {
+		bootargs = "console=ttyTCU0,115200";
+	};
+
+	/* Fixed 2.3V regulator for external SD card slot */
+	fixed-regulators {
+		ap2306gn_3v3_sd: ap2306gn_3v3_sd {
+			compatible = "regulator-fixed";
+			regulator-name = "ap2306gn-3v3-sd";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio TEGRA194_MAIN_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			status = "okay";
+		};
+	};
+
+	/* Custom pinmux configurations for 40-pin expansion header */
+	pinmux@c302000 {
+		status = "okay";
+		touch_clk_pcc4 {
+			nvidia,pins = "touch_clk_pcc4";
+			nvidia,function = "rsvd2";
+			nvidia,pull = <TEGRA_PIN_PULL_UP>;
+			nvidia,tristate = <TEGRA_PIN_ENABLE>;
+			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+		};
+	};
+
+	pinmux@2430028 {
+		status = "okay";
+		soc_gpio41_pq5 {
+			nvidia,pins = "soc_gpio41_pq5";
+			nvidia,function = "rsvd2";
+			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+			nvidia,tristate = <TEGRA_PIN_DISABLE>;
+			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+			nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+		};
+	};
+
+	pinmux@2430000 {
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdr40_pinmux>;
+
+		hdr40_pinmux: header-40pin-pinmux {
+			pin7 {
+				nvidia,pins = "aud_mclk_ps4";
+				nvidia,function = "aud";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			pin11 {
+				nvidia,pins = "uart1_rts_pr4";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,lpdr = <0x0>;
+			};
+			pin12 {
+				nvidia,pins = "dap5_sclk_pt5";
+				nvidia,function = "i2s5";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pin35 {
+				nvidia,pins = "dap5_fs_pu0";
+				nvidia,function = "i2s5";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pin36 {
+				nvidia,pins = "uart1_cts_pr5";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,lpdr = <0x0>;
+			};
+			pin38 {
+				nvidia,pins = "dap5_din_pt7";
+				nvidia,function = "i2s5";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pin40 {
+				nvidia,pins = "dap5_dout_pt6";
+				nvidia,function = "i2s5";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+		};
+	};
+
+	/* Configure i2c bus clock to 400kHz for carrier board peripherals */
+	i2c@3160000 {
+		clock-frequency = <400000>;
+		status = "okay";
+	};
+
+	/* SDMMC3 for external user SD card slot with dedicated 3.3V power */
+	sdhci@3440000 {
+		uhs-mask = <0x78>;
+		mmc-ocr-mask = <0x0>;
+		cd-inverted;
+		cd-gpios = <&gpio_aon TEGRA194_AON_GPIO(CC, 4) GPIO_ACTIVE_LOW>;
+		nvidia,cd-wakeup-capable;
+		vmmc-supply = <&ap2306gn_3v3_sd>;
+		status = "okay";
+	};
+
+	/* Disable fan and tachometer hardware not populated on SE70 carrier board */
+	pwm-fan {
+		status = "disabled";
+	};
+	thermal-fan-est {
+		status = "disabled";
+	};
+	tachometer@39c0000 {
+		status = "disabled";
+	};
+	pwm@c340000 {
+		status = "disabled";
+	};
+	pwm@3280000 {
+		status = "disabled";
+	};
+	pwm@32c0000 {
+		status = "disabled";
+	};
+	pwm@32d0000 {
+		status = "disabled";
+	};
+	pwm@32f0000 {
+		status = "disabled";
+	};
+	generic_pwm_tachometer {
+		status = "disabled";
+	};
+
+	/* Disable unused SPI interfaces on 40-pin header */
+	spi@3210000 {
+		status = "disabled";
+	};
+	spi@3230000 {
+		status = "disabled";
+	};
+};
-- 
2.43.0

Re: [PATCH 2/2] arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
- [High] Peripheral overrides and configuration nodes are incorrectly placed at the root of the device tree, failing to override the actual bus children.
- [High] The `fixed-regulators` container lacks the `compatible = "simple-bus"` property, preventing its children from probing.
- [High] The `cd-inverted` property combined with `GPIO_ACTIVE_LOW` causes a double-inversion of the SD card detect signal.
- [Medium] Use of downstream Linux-for-Tegra (L4T) device tree properties that are invalid in mainline.
- [Low] Device tree node names use underscores instead of hyphens.
- [Low] Mismatch between inline code comment and regulator voltage configuration.
--

commit ce1b543209b572c99dba284d418dec1c8ce39718
Author: Jiqi Li <lijq9@lenovo.com>

arm64: tegra: Add Lenovo ThinkEdge SE70 carrier board DTS

ThinkEdge SE70 is a fanless industrial edge gateway built around
NVIDIA Tegra194 Xavier NX SOM. This patch adds a standalone device
tree file describing core carrier board peripherals:
- Custom 40-pin header pinmux configuration
- External SD card slot with dedicated 3.3V fixed regulator

No fan, PWM, tachometer, extra camera/spi peripherals are present
on this passively cooled platform, so unused nodes are explicitly
disabled following mainline device tree best practices.

Static verification passed: dt_binding_check and dtbs compilation
complete without errors.

[ ... ]

> diff --git a/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
> new file mode 100644
> index 0000000000000..075e057c90954
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts
> @@ -0,0 +1,167 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +
> +#include "tegra194-p3668-0001.dtsi"
> +#include "tegra194-p3509-0000.dtsi"
> +
> +/ {
> +	model = "Lenovo ThinkEdge SE70";
> +	compatible = "lenovo,thinkedge-se70", "nvidia,p3509-0000+p3668-0001", "nvidia,tegra194";
> +
> +	chosen {
> +		bootargs = "console=ttyTCU0,115200";
> +	};
> +
> +	/* Fixed 2.3V regulator for external SD card slot */
[Severity: Low]
Is this comment accurate? It mentions a 2.3V regulator, but the configuration
properties below (regulator-min-microvolt and regulator-max-microvolt) enforce
3.3V.

> +	fixed-regulators {
[Severity: High]
Does this fixed-regulators container need a compatible = "simple-bus" property?
Without a recognized bus compatible string, of_platform_populate() won't
recurse into this node at boot. This would prevent the ap2306gn_3v3_sd child
regulator from probing, causing the SDHCI controller requesting it to fail with
-EPROBE_DEFER.

> +		ap2306gn_3v3_sd: ap2306gn_3v3_sd {
[Severity: Low]
Should this node name use hyphens instead of underscores (e.g.,
ap2306gn-3v3-sd) to comply with Devicetree specification naming rules and avoid
node_name_chars warnings during compilation?

> +			compatible = "regulator-fixed";
> +			regulator-name = "ap2306gn-3v3-sd";
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3300000>;

[ ... ]

> +	/* Custom pinmux configurations for 40-pin expansion header */
> +	pinmux@c302000 {
[Severity: High]
Are these peripheral and pinmux configuration nodes incorrectly placed at the
root level of the device tree (/ {}) rather than being children of the SoC bus?
Placing nodes like pinmux@..., i2c@..., and sdhci@... directly under the root
creates disconnected dummy nodes instead of overriding the actual bus-attached
controllers, causing these intended configurations to be completely ignored.

> +		status = "okay";
> +		touch_clk_pcc4 {

[ ... ]

> +	pinmux@2430028 {
> +		status = "okay";
> +		soc_gpio41_pq5 {
> +			nvidia,pins = "soc_gpio41_pq5";
> +			nvidia,function = "rsvd2";
> +			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
> +			nvidia,tristate = <TEGRA_PIN_DISABLE>;
> +			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
> +			nvidia,lpdr = <TEGRA_PIN_DISABLE>;
> +			nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
[Severity: Medium]
Are nvidia,lpdr and nvidia,io-high-voltage downstream Linux-for-Tegra (L4T)
properties? They don't appear to exist in the mainline devicetree bindings,
which means they will be ignored by upstream drivers and fail dt_binding_check
schema validation.

> +		};
> +	};

[ ... ]

> +	/* SDMMC3 for external user SD card slot with dedicated 3.3V power */
> +	sdhci@3440000 {
[Severity: High]
Similar to the pinmux nodes above, is this sdhci node placed as a direct child
of the root (/ {}) instead of the SoC bus? This creates a new orphaned node
rather than overriding the actual bus-attached SDHCI controller.

> +		uhs-mask = <0x78>;
> +		mmc-ocr-mask = <0x0>;
[Severity: Medium]
Are uhs-mask and mmc-ocr-mask valid mainline properties? Like the pinmux
properties above, these appear to be downstream L4T properties that will fail
dt_binding_check schema validation.

> +		cd-inverted;
> +		cd-gpios = <&gpio_aon TEGRA194_AON_GPIO(CC, 4) GPIO_ACTIVE_LOW>;
[Severity: High]
Does combining the cd-inverted property with GPIO_ACTIVE_LOW in cd-gpios cause
a logical double inversion of the SD card detect signal? The GPIO subsystem
will invert the active-low physical signal, and then the MMC core will invert
that result again due to cd-inverted. This could mean an inserted card is seen
as removed and vice versa, breaking card hotplugging.

> +		nvidia,cd-wakeup-capable;
[Severity: Medium]
Is nvidia,cd-wakeup-capable another downstream property unsupported in
mainline?

> +		vmmc-supply = <&ap2306gn_3v3_sd>;
> +		status = "okay";
> +	};

[ ... ]

> +	pwm@32f0000 {
> +		status = "disabled";
> +	};
> +	generic_pwm_tachometer {
[Severity: Low]
Should this node name use hyphens instead of underscores (e.g.,
generic-pwm-tachometer) to avoid devicetree specification violations and
node_name_chars warnings?

> +		status = "disabled";
> +	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260626010950.459899-1-lijq9@lenovo.com?part=2