Re: [PATCH v2 2/3] net: ethernet: ti: am65-cpsw: Fix MAC configuration for SGMII mode

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The MAC is unconditionally forced into SGMII MASTER mode and hardcoded to advertise a 1000 Mbps Full-Duplex link, breaking 10/100 Mbps support and standard MAC-to-PHY connections.
- [High] Moving the write to `AM65_CPSW_SGMII_CONTROL_REG` inside the SGMII-only block inadvertently disables auto-negotiation for USXGMII and QSGMII modes.
--

commit f84ed4938492bf35df72f44323de46f0c35177e0
Author: Gokul Praveen <g-praveen@ti.com>

net: ethernet: ti: am65-cpsw: Fix MAC configuration for SGMII mode

This modifies the CPSW_SGMII_MR_ADV_ABILITY_REG to update the MAC
configuration of the CPSW Ethernet Switch in SGMII mode. It configures
the MAC in master mode as per the CPSGMII Module specification.

> diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
> index 7ac75fc8cdcf4..df99a80dbfe1e 100644
> --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
> +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c

[ ... ]

> @@ -2063,8 +2064,10 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in
>  
>  	if (common->pdata.extra_modes & BIT(state->interface)) {
>  		if (state->interface == PHY_INTERFACE_MODE_SGMII) {
> -			writel(ADVERTISE_SGMII,
> -			       port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);
> +			writel(ADVERTISE_SGMII | LPA_SGMII_1000FULL | LPA_SGMII_LINK,
> +				port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);
> +			writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE|AM65_CPSW_SGMII_CONTROL_MASTER,
> +				port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);

[Severity: High]
Does am65_cpsw_nuss_mac_config() now hardcode the SGMII advertisement to
1000 Mbps Full-Duplex while ignoring the dynamic link parameters in
state->speed and state->duplex?

If the MAC is unconditionally forced into SGMII MASTER mode and forced to
advertise a 1000 Mbps full-duplex link, could this break 10 Mbps and 100 Mbps
connections, as well as standard MAC-to-PHY connections where the PHY expects
to be the SGMII Master?

>  			cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN);
>  		} else {
>  			cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN);
> @@ -2078,8 +2081,6 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in
>  					CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN);
>  		}
>  
> -		writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,
> -		       port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);

[Severity: High]
Will removing this write and moving it inside the SGMII-only block disable
auto-negotiation for USXGMII and QSGMII modes?

Since this unconditional write enabled auto-negotiation for all extra modes,
moving it to the PHY_INTERFACE_MODE_SGMII branch means it is never configured
when state->interface is USXGMII or QSGMII, which might prevent link
establishment.

>  	}
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260629102308.56616-1-g-praveen@ti.com?part=2