Re: [PATCH v5 1/3] dt-bindings: spi: Add spi,device-addr peripheral property

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Architectural misplacement of the `spi,device-addr` property and incorrect hardware modeling for shared chip selects.
- [Low] Invalid property name formatting (`spi,device-addr`) causing schema validation failure.
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commit a13113dfcdf0e6c76170858ecffc2c11d4c536cf
Author: Janani Sunil <janani.sunil@analog.com>

dt-bindings: spi: Add spi,device-addr peripheral property

Some SPI devices support sharing a single chip select across multiple
physical chips by encoding a device address in the SPI frame itself.
Add a generic spi,device-addr property to document this per-peripheral
address. This property belongs in channel or sub-device nodes of
peripherals that use this addressing scheme.

> diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
> index 880a9f6245667..3774e80183555 100644
> --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
> +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
> @@ -142,6 +142,11 @@ properties:
>      minItems: 2
>      maxItems: 4
>  
> +  spi,device-addr:

[Severity: Low]
Does this property name pass make dt_binding_check?

Since spi is not a registered vendor in vendor-prefixes.yaml, the comma
syntax typically causes a validation failure. Should this regression be fixed
by using a hyphen instead for a subsystem generic property, such as
spi-device-addr?

[Severity: High]
Does this architectural approach correctly model the hardware?

By placing this property in spi-peripheral-props.yaml, it applies to direct
children of the SPI controller, yet the commit message notes it belongs in
channel or sub-device nodes.

Standard Device Tree architecture generally models a shared chip select bus as a
parent node (with #address-cells and #size-cells) and the individual
chips as child nodes using the standard reg property.

Does using a custom addressing property on sub-channels bypass the standard
DT bus addressing model?

> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Device address used when multiple peripherals share a single chip select.
> +

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Sashiko AI review · https://sashiko.dev/#/patchset/20260701-ad5529r-driver-v5-0-ed087900e642@analog.com?part=1