[PATCH v4 net-next 0/2] Add multilink SERDES configuration support

[PATCH v4 net-next 0/2] Add multilink SERDES configuration support

[Gokul Praveen]

Add multilink SERDES configuration support for SERDES0,SERDES1
SERDES2 and SERDES4 node on TI J784S4 EVM.

This patch series add multilink SERDES configurations support 
for SERDES0,SERDES1 SERDES2 and SERDES4 node on TI J784S4 EVM 
by adding the PLL1 refclk.

Gokul Praveen (2):
  dt-bindings: phy: cadence-torrent: Update property values to support 3
    clocks
  arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node

 .../bindings/phy/phy-cadence-torrent.yaml        | 16 ++++++++++++----
 .../dts/ti/k3-j784s4-j742s2-main-common.dtsi     |  9 ++++++---
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi       |  3 ++-
 3 files changed, 20 insertions(+), 8 deletions(-)

-- 
2.34.1

[PATCH v4 net-next 1/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

[Gokul Praveen]

Update maxItems value of "clocks" property to 3 as description of
this parameter already indicates 3 clocks(refclk,pll1_refclk(optional)
and phy_en_refclk(optional)).

Update the maxItems and items value of "clock-names" property with multiple
combination of clock-names possible since pll1_refclk and phy_en_refclk are
optional clocks.

Signed-off-by: Gokul Praveen <g-praveen@ti.com>
---
 .../bindings/phy/phy-cadence-torrent.yaml        | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
index 9af39b33646a..96c664d50629 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -34,7 +34,7 @@ properties:
 
   clocks:
     minItems: 1
-    maxItems: 2
+    maxItems: 3
     description:
       PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
       pll1_refclk is optional and used for multi-protocol configurations requiring
@@ -45,9 +45,17 @@ properties:
 
   clock-names:
     minItems: 1
-    items:
-      - const: refclk
-      - enum: [ pll1_refclk, phy_en_refclk ]
+    maxItems: 3
+    oneOf:
+      - items:
+          - const: refclk
+      - items:
+          - const: refclk
+          - enum: [ pll1_refclk, phy_en_refclk ]
+      - items:
+          - const: refclk
+          - const: pll1_refclk
+          - const: phy_en_refclk
 
   reg:
     minItems: 1
-- 
2.34.1

Re: [PATCH v4 net-next 1/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

[Krzysztof Kozlowski]

On Wed, Jul 01, 2026 at 07:54:56PM +0530, Gokul Praveen wrote:
> Update maxItems value of "clocks" property to 3 as description of
> this parameter already indicates 3 clocks(refclk,pll1_refclk(optional)
> and phy_en_refclk(optional)).

But what if description is wrong? You need to provide rationale why you
are doing it and you cannot use existing code alone as that rationale,
because as you pointed out - existing code is not fully correct.

> 
> Update the maxItems and items value of "clock-names" property with multiple
> combination of clock-names possible since pll1_refclk and phy_en_refclk are
> optional clocks.

Why? You need to describe why you are doing this, not what you are
doing.

> 
> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
> ---
>  .../bindings/phy/phy-cadence-torrent.yaml        | 16 ++++++++++++----
>  1 file changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> index 9af39b33646a..96c664d50629 100644
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -34,7 +34,7 @@ properties:
>  
>    clocks:
>      minItems: 1
> -    maxItems: 2
> +    maxItems: 3
>      description:
>        PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
>        pll1_refclk is optional and used for multi-protocol configurations requiring
> @@ -45,9 +45,17 @@ properties:
>  
>    clock-names:
>      minItems: 1
> -    items:
> -      - const: refclk
> -      - enum: [ pll1_refclk, phy_en_refclk ]
> +    maxItems: 3

Drop

> +    oneOf:
> +      - items:
> +          - const: refclk
> +      - items:
> +          - const: refclk
> +          - enum: [ pll1_refclk, phy_en_refclk ]

Drop these, pointless. You were supposed to grow existing syntax.

> +      - items:
> +          - const: refclk
> +          - const: pll1_refclk

So here is the enum.

> +          - const: phy_en_refclk

And this stays.

You make changes which do not make the binding better and are not
explained in commit msg. Focus on WHY you are doing things and also
explain WHY you did such complicated syntax (if you insist on rewriting
correct code into something odd we do not expect).

Best regards,
Krzysztof

Re: [PATCH v4 net-next 1/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

[Gokul Praveen]

Hi Krzystof,

On 02/07/26 11:53, Krzysztof Kozlowski wrote:
> On Wed, Jul 01, 2026 at 07:54:56PM +0530, Gokul Praveen wrote:
>> Update maxItems value of "clocks" property to 3 as description of
>> this parameter already indicates 3 clocks(refclk,pll1_refclk(optional)
>> and phy_en_refclk(optional)).
> But what if description is wrong? You need to provide rationale why you
> are doing it and you cannot use existing code alone as that rationale,
> because as you pointed out - existing code is not fully correct.

The description is correct because not all device may have 2 input  
reference clocks , hence keeping the requirement of the 2nd reference 
clock(pll1_refclk) optional.

Just as a note: phy_en_refclk is an output clock.

In those cases the multilink serdes configurations requiring 2 different 
input reference clocks will not work due to the limitation of having 
only 1 clock.

However, when it comes to devices where 2 different input reference 
clocks are supported and a multilink serdes configuration is 
needed(where the links require separate reference clocks for each 
protocol so as to cater to the  different clocking speed requirements of 
these links).

Hence, in this case ,2 different input clocks are needed so as to cater 
to 2 different clock speeds.

For eg: In the USXGMII+SGMII multilink serdes configuration which I had 
tested, it failed because

USXGMII requires an input clock speed of 156.25 Mhz and SGMII protocol 
requires an input clock speed of 100 Mhz.

But, since there was only one input clock(refclk) mentioned in the 
clocks and clock-name parameter , this multilink serdes configuration 
failed.

Hence, to make it work, the pll1_refclk had to be added which provided a 
clock speed of 156.25 Mhz for USXGMI and the refclk provided

a clock speed of 100 Mhz  for SGMII.

>> Update the maxItems and items value of "clock-names" property with multiple
>> combination of clock-names possible since pll1_refclk and phy_en_refclk are
>> optional clocks.
> Why? You need to describe why you are doing this, not what you are
> doing.
Sure , Krzysztof, I will be careful about that and prioritize that in 
the commit message.
>> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
>> ---
>>   .../bindings/phy/phy-cadence-torrent.yaml        | 16 ++++++++++++----
>>   1 file changed, 12 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>> index 9af39b33646a..96c664d50629 100644
>> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>> @@ -34,7 +34,7 @@ properties:
>>   
>>     clocks:
>>       minItems: 1
>> -    maxItems: 2
>> +    maxItems: 3
>>       description:
>>         PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
>>         pll1_refclk is optional and used for multi-protocol configurations requiring
>> @@ -45,9 +45,17 @@ properties:
>>   
>>     clock-names:
>>       minItems: 1
>> -    items:
>> -      - const: refclk
>> -      - enum: [ pll1_refclk, phy_en_refclk ]
>> +    maxItems: 3
> Drop
Sure, i will do that Krzysztof.
>> +    oneOf:
>> +      - items:
>> +          - const: refclk
>> +      - items:
>> +          - const: refclk
>> +          - enum: [ pll1_refclk, phy_en_refclk ]
> Drop these, pointless. You were supposed to grow existing syntax.
>
>> +      - items:
>> +          - const: refclk
>> +          - const: pll1_refclk
> So here is the enum.
>
>> +          - const: phy_en_refclk
> And this stays.
>
> You make changes which do not make the binding better and are not
> explained in commit msg. Focus on WHY you are doing things and also
> explain WHY you did such complicated syntax (if you insist on rewriting
> correct code into something odd we do not expect).

So, the reason I added the oneOf property is to support the following 
combinations because pll1_refclk and phy_en_refclk are optional clocks. 
With the earlier enum , only either of pll1_refclk or phy_en_refclk

can be used and both cannot be used at the same time.

Combination 1: refclk

Combination 2 : refclk, pll1_refclk

Combination 3: reclk, phy_en_refclk

Combination 4: refclk, pll1_refclk, phy_en_refclk


Please feel free to suggest any alternative solution to support these 
combinations .

>
> Best regards,
> Krzysztof
>
>

Re: [PATCH v4 net-next 1/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

[Krzysztof Kozlowski]

On 02/07/2026 09:35, Gokul Praveen wrote:
> Hi Krzystof,
> 
> On 02/07/26 11:53, Krzysztof Kozlowski wrote:
>> On Wed, Jul 01, 2026 at 07:54:56PM +0530, Gokul Praveen wrote:
>>> Update maxItems value of "clocks" property to 3 as description of
>>> this parameter already indicates 3 clocks(refclk,pll1_refclk(optional)
>>> and phy_en_refclk(optional)).
>> But what if description is wrong? You need to provide rationale why you
>> are doing it and you cannot use existing code alone as that rationale,
>> because as you pointed out - existing code is not fully correct.
> 
> The description is correct because not all device may have 2 input  

I do not see how you proved it in the commit msg.

> reference clocks , hence keeping the requirement of the 2nd reference 
> clock(pll1_refclk) optional.
> 
> Just as a note: phy_en_refclk is an output clock.

output clocks do not go to input clocks property.

> 
> In those cases the multilink serdes configurations requiring 2 different 
> input reference clocks will not work due to the limitation of having 
> only 1 clock.
> 
> However, when it comes to devices where 2 different input reference 
> clocks are supported and a multilink serdes configuration is 
> needed(where the links require separate reference clocks for each 
> protocol so as to cater to the  different clocking speed requirements of 
> these links).
> 
> Hence, in this case ,2 different input clocks are needed so as to cater 
> to 2 different clock speeds.
> 
> For eg: In the USXGMII+SGMII multilink serdes configuration which I had 
> tested, it failed because
> 
> USXGMII requires an input clock speed of 156.25 Mhz and SGMII protocol 
> requires an input clock speed of 100 Mhz.
> 
> But, since there was only one input clock(refclk) mentioned in the 
> clocks and clock-name parameter , this multilink serdes configuration 
> failed.
> 
> Hence, to make it work, the pll1_refclk had to be added which provided a 
> clock speed of 156.25 Mhz for USXGMI and the refclk provided
> 
> a clock speed of 100 Mhz  for SGMII.
> 
>>> Update the maxItems and items value of "clock-names" property with multiple
>>> combination of clock-names possible since pll1_refclk and phy_en_refclk are
>>> optional clocks.
>> Why? You need to describe why you are doing this, not what you are
>> doing.
> Sure , Krzysztof, I will be careful about that and prioritize that in 
> the commit message.
>>> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
>>> ---
>>>   .../bindings/phy/phy-cadence-torrent.yaml        | 16 ++++++++++++----
>>>   1 file changed, 12 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>>> index 9af39b33646a..96c664d50629 100644
>>> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>>> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>>> @@ -34,7 +34,7 @@ properties:
>>>   
>>>     clocks:
>>>       minItems: 1
>>> -    maxItems: 2
>>> +    maxItems: 3
>>>       description:
>>>         PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
>>>         pll1_refclk is optional and used for multi-protocol configurations requiring
>>> @@ -45,9 +45,17 @@ properties:
>>>   
>>>     clock-names:
>>>       minItems: 1
>>> -    items:
>>> -      - const: refclk
>>> -      - enum: [ pll1_refclk, phy_en_refclk ]
>>> +    maxItems: 3
>> Drop
> Sure, i will do that Krzysztof.
>>> +    oneOf:
>>> +      - items:
>>> +          - const: refclk
>>> +      - items:
>>> +          - const: refclk
>>> +          - enum: [ pll1_refclk, phy_en_refclk ]
>> Drop these, pointless. You were supposed to grow existing syntax.
>>
>>> +      - items:
>>> +          - const: refclk
>>> +          - const: pll1_refclk
>> So here is the enum.
>>
>>> +          - const: phy_en_refclk
>> And this stays.
>>
>> You make changes which do not make the binding better and are not
>> explained in commit msg. Focus on WHY you are doing things and also
>> explain WHY you did such complicated syntax (if you insist on rewriting
>> correct code into something odd we do not expect).
> 
> So, the reason I added the oneOf property is to support the following 
> combinations because pll1_refclk and phy_en_refclk are optional clocks. 
> With the earlier enum , only either of pll1_refclk or phy_en_refclk
> 
> can be used and both cannot be used at the same time.
> 
> Combination 1: refclk
> 
> Combination 2 : refclk, pll1_refclk
> 
> Combination 3: reclk, phy_en_refclk
> 
> Combination 4: refclk, pll1_refclk, phy_en_refclk
> 
> 
> Please feel free to suggest any alternative solution to support these 
> combinations .

I already did. Read the feedback carefully.

Best regards,
Krzysztof

Re: [PATCH v4 net-next 1/2] dt-bindings: phy: cadence-torrent: Update property values to support 3 clocks

[Gokul Praveen]

Hi Krzysztof,

On 02/07/26 11:53, Krzysztof Kozlowski wrote:
> On Wed, Jul 01, 2026 at 07:54:56PM +0530, Gokul Praveen wrote:
>> Update maxItems value of "clocks" property to 3 as description of
>> this parameter already indicates 3 clocks(refclk,pll1_refclk(optional)
>> and phy_en_refclk(optional)).
> But what if description is wrong? You need to provide rationale why you
> are doing it and you cannot use existing code alone as that rationale,
> because as you pointed out - existing code is not fully correct.
>
>> Update the maxItems and items value of "clock-names" property with multiple
>> combination of clock-names possible since pll1_refclk and phy_en_refclk are
>> optional clocks.
> Why? You need to describe why you are doing this, not what you are
> doing.
>
Would the below commit description be good enough ? Please feel free to 
give any suggestions on this:

''

dt-bindings: phy: cadence-torrent: Update property values to support 3 
clocks

     Increase the maxItems value of "clocks" property to 3 to support
     2 input clocks(refclk,pll1_refclk) and 1 output clock(phy_en_refclk).

     For multilink SERDES configurations where the links require 2 
different input clock speeds,
     2 different input reference clocks and 1 output clock is needed so 
as to cater to this requirement.

     For eg: Considering the USXGMII+SGMII multilink SERDES 
configuration usecase ,
     having only 1 input reference clock fails because USXGMII requires 
an input clock speed of 156.25 Mhz and
     SGMII protocol requires an input clock speed of 100 Mhz.

     Since one input reference clock(refclk) alone cannot cater to the 2 
different clock speed requirements
     of these protocols, the second input reference clock(pll1_refclk) 
has to be added.


     Signed-off-by: Gokul Praveen <g-praveen@ti.com>
''

>> Signed-off-by: Gokul Praveen <g-praveen@ti.com>
>> ---
>>   .../bindings/phy/phy-cadence-torrent.yaml        | 16 ++++++++++++----
>>   1 file changed, 12 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>> index 9af39b33646a..96c664d50629 100644
>> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>> @@ -34,7 +34,7 @@ properties:
>>   
>>     clocks:
>>       minItems: 1
>> -    maxItems: 2
>> +    maxItems: 3
>>       description:
>>         PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
>>         pll1_refclk is optional and used for multi-protocol configurations requiring
>> @@ -45,9 +45,17 @@ properties:
>>   
>>     clock-names:
>>       minItems: 1
>> -    items:
>> -      - const: refclk
>> -      - enum: [ pll1_refclk, phy_en_refclk ]
>> +    maxItems: 3
> Drop
sure krzysztof.
>> +    oneOf:
>> +      - items:
>> +          - const: refclk
>> +      - items:
>> +          - const: refclk
>> +          - enum: [ pll1_refclk, phy_en_refclk ]
> Drop these, pointless. You were supposed to grow existing syntax.
>
Sure Krzysztof
>> +      - items:
>> +          - const: refclk
>> +          - const: pll1_refclk
> So here is the enum.
>
>> +          - const: phy_en_refclk
>>
>> And this stays.

SUre Krzysztof

>>
>> You make changes which do not make the binding better and are not
>> explained in commit msg. Focus on WHY you are doing things and also
>> explain WHY you did such complicated syntax (if you insist on rewriting
>> correct code into something odd we do not expect).
>>
>> Best regards,
>> Krzysztof

Best Regards

Gokul Praveen

>

[PATCH v4 net-next 2/2] arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node

[Gokul Praveen]

Add PLL1 refclk to "clocks" and "clock-names" parameter of SERDES0,
SERDES1,SERDES2 and SERDES4 node as "assigned clocks" parameter has PLL1
and serdes multilink configuration fails without PLL1.

Signed-off-by: Gokul Praveen <g-praveen@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 9 ++++++---
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi               | 3 ++-
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index c2636e624f18..e5224bd7f538 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -1149,8 +1149,9 @@ serdes0: serdes@5060000 {
 			resets = <&serdes_wiz0 0>;
 			reset-names = "torrent_reset";
 			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
 				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
-			clock-names = "refclk", "phy_en_refclk";
+			clock-names = "refclk",	"pll1_refclk", "phy_en_refclk";
 			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
 					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
 					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
@@ -1186,8 +1187,9 @@ serdes1: serdes@5070000 {
 			resets = <&serdes_wiz1 0>;
 			reset-names = "torrent_reset";
 			clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
 				 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
-			clock-names = "refclk", "phy_en_refclk";
+			clock-names = "refclk",	"pll1_refclk", "phy_en_refclk";
 			assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
 					  <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
 					  <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
@@ -1229,8 +1231,9 @@ serdes4: serdes@5050000 {
 			resets = <&serdes_wiz4 0>;
 			reset-names = "torrent_reset";
 			clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
 				 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
-			clock-names = "refclk", "phy_en_refclk";
+			clock-names = "refclk",	"pll1_refclk", "phy_en_refclk";
 			assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
 					  <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
 					  <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 78fcd0c40abc..53109e2fe527 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -122,8 +122,9 @@ serdes2: serdes@5020000 {
 			resets = <&serdes_wiz2 0>;
 			reset-names = "torrent_reset";
 			clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
 				 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
-			clock-names = "refclk", "phy_en_refclk";
+			clock-names = "refclk",	"pll1_refclk", "phy_en_refclk";
 			assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
 					  <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
 					  <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
-- 
2.34.1

Re: [PATCH v4 net-next 2/2] arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The Cadence Torrent PHY multilink configuration will fail on other K3 platforms (e.g., J721S2) due to a missing pll1_refclk property in identical serdes nodes.
--

commit cad292e544578dc0fc4b900abd68b229a97dc116
Author: Gokul Praveen <g-praveen@ti.com>

arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node

This commit adds the PLL1 reference clock to the clocks and clock-names
parameters of the SERDES nodes for the J784S4 and J742S2 SoCs. This resolves
an issue where serdes multilink configurations fail without PLL1.

> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> index c2636e624f18b..e5224bd7f5383 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
> @@ -1149,8 +1149,9 @@ serdes0: serdes@5060000 {
>  			resets = <&serdes_wiz0 0>;
>  			reset-names = "torrent_reset";
>  			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> +				 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
>  				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> -			clock-names = "refclk", "phy_en_refclk";
> +			clock-names = "refclk",	"pll1_refclk", "phy_en_refclk";

[Severity: High]
This isn't a bug introduced by this patch, but does the same multilink
configuration failure occur on other K3 platforms like J721S2?

Looking at serdes0 in arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi, it lacks
the pll1_refclk property in the clocks array:

    clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
             <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
    clock-names = "refclk", "phy_en_refclk";

When a multilink configuration is requested on these platforms (e.g., PCIe on
lane 0 and SGMII on lane 1), will the phy-cadence-torrent driver fail to
enable the PLL1 reference clock?

Could this cause essential peripheral initialization to fail when the
PHY is unable to lock PLL1?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260701142457.81874-1-g-praveen@ti.com?part=2