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From: sashiko-bot@kernel.org
To: "Manaf Meethalavalappu Pallikunhi" <manaf.pallikunhi@oss.qualcomm.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org
Subject: Re: [PATCH v3 1/4] dt-bindings: power: Add common power limit controller schema
Date: Thu, 02 Jul 2026 17:44:32 +0000	[thread overview]
Message-ID: <20260702174432.D24CA1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260702-qcom_spel_driver_upstream-v3-1-434d50f0c5b0@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] YAML formatting disruption due to missing block scalar indicator in description
--

commit 10d28ed72d993f07d4586a72f1c37a8d7f35d2eb
Author: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>

dt-bindings: power: Add common power limit controller schema

This commit adds a common device tree binding schema for power limit
controller devices. It defines the base properties and node naming pattern
for hardware blocks that enforce power consumption limits on SoC power domains.

> diff --git a/Documentation/devicetree/bindings/power/limits/power-limit-controller.yaml b/Documentation/devicetree/bindings/power/limits/power-limit-controller.yaml
> new file mode 100644
> index 0000000000000..a00548fdc79e2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/limits/power-limit-controller.yaml
[ ... ]
> +maintainers:
> +  - Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
> +
> +description:

[Severity: Low]
Should this description field include a block scalar indicator (like | or >)? 

Without it, the YAML parser will treat the multi-paragraph text as a plain
scalar. This will fold the adjacent lines and the bulleted list below into a
single run-on sentence, which disrupts the formatting in the generated
documentation.

> +  Power limit controllers are hardware blocks that enforce power consumption
> +  limits on SoC power domains to prevent thermal overload, maintain system
> +  stability, and comply with platform power budgets.
> +
> +  These controllers typically provide
> +    - Hardware-enforced power capping for one or more power domains
> +    - Configurable power limits (e.g., sustained, burst, peak)
> +    - Time window controls for power averaging
> +    - Energy or power monitoring and reporting capabilities
> +    - Power balancing algorithms across domains

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260702-qcom_spel_driver_upstream-v3-0-434d50f0c5b0@oss.qualcomm.com?part=1

  reply	other threads:[~2026-07-02 17:44 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-02 17:22 [PATCH v3 0/4] Add Qualcomm SPEL powercap driver Manaf Meethalavalappu Pallikunhi
2026-07-02 17:22 ` [PATCH v3 1/4] dt-bindings: power: Add common power limit controller schema Manaf Meethalavalappu Pallikunhi
2026-07-02 17:44   ` sashiko-bot [this message]
2026-07-03  6:20   ` Krzysztof Kozlowski
2026-07-02 17:22 ` [PATCH v3 2/4] dt-bindings: power: limits: Describe Qualcomm SPEL hardware Manaf Meethalavalappu Pallikunhi
2026-07-02 17:30   ` sashiko-bot
2026-07-03  6:21   ` Krzysztof Kozlowski
2026-07-02 17:22 ` [PATCH v3 3/4] powercap: qcom: Add SPEL powercap driver Manaf Meethalavalappu Pallikunhi
2026-07-02 17:36   ` sashiko-bot
2026-07-03  6:24   ` Krzysztof Kozlowski
2026-07-02 17:22 ` [PATCH v3 4/4] arm64: dts: qcom: glymur: Enable " Manaf Meethalavalappu Pallikunhi

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