Re: [PATCH v6 08/12] clk: zte: Introduce a driver for zx297520v3 top clocks

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The PLLs `unknownpll` and `dpll` will be improperly orphaned by the common clock framework if the hardware boots with alternate parent indices.
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commit b48ea22652716b42ff4252581eeabf1b55dc958b
Author: Stefan Dösinger <stefandoesinger@gmail.com>

clk: zte: Introduce a driver for zx297520v3 top clocks

This commit introduces a driver for the ZTE zx297520v3 top clock
register space. It provides clock control for core devices including
PLLs, the AHB bus, timers, and the USB controller.

> diff --git a/drivers/clk/zte/clk-zx297520v3.c b/drivers/clk/zte/clk-zx297520v3.c
> new file mode 100644
> index 0000000000000..6fc98f98cf9c8
> --- /dev/null
> +++ b/drivers/clk/zte/clk-zx297520v3.c
[ ... ]
> +static const char * const dpll_parents[] = {
> +	"unknownpll_d2",
> +	"osc26m",
> +};

[Severity: Medium]
The comment further below for dpll mentions it accepts parent values 0, 1, 2,
and 3. If the bootloader leaves the hardware configured to use parent index 2
or 3, will the common clock framework treat this as an out-of-bounds index and
orphan the clock? 

If CCF treats it as orphaned, the parent rate passed to the recalc_rate hook
will be 0, leading to a 0 Hz clock rate for dpll and all its descendants.
Could we expand this array to include the alias parents to prevent this?

[ ... ]
> +	/* Default value 0x4834902d. Feeds dpll. 46.08 MHz. Bit 25 can be set, so two parents are
> +	 * possible. It looks like both values select the 26 MHz oscillator though.
> +	 */
> +	{
> +		.id = 0,
> +		.name = "unknownpll",
> +		.parents = clk_main,
> +		.num_parents = ARRAY_SIZE(clk_main),

[Severity: Medium]
Since clk_main only has one entry, num_parents will be 1. If bit 25 is set by
the bootloader, the hardware could return parent index 1. 

Would that cause the same CCF orphaning issue here, where an out-of-bounds
index results in a 0 Hz calculated rate for unknownpll and dependent devices?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260702-zx29clk-v6-0-377b704f80c4@gmail.com?part=8